src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013, 2014 Vladimir Serbinenko
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 or (at your option)
   9  *  any later version of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <arch/io.h>
  18 #include <console/console.h>
  19 #include <delay.h>
  20 #include <device/device.h>
  21 #include <string.h>
  22
  23 #include <drivers/intel/gma/edid.h>
  24 #include <drivers/intel/gma/i915.h>
  25 #include "gma.h"
  26 #include "chip.h"
  27 #include <pc80/vga.h>
  28 #include <pc80/vga_io.h>
  29 #include <device/pci_def.h>
  30 #include <device/pci_rom.h>
  31
  32 static void train_link(u8 *mmio)
  33 {
  34         /* Clear interrupts. */
  35         write32(mmio + DEIIR, 0xffffffff);
  36
  37         write32(mmio + 0xf000c, 0x2040);
  38         write32(mmio + 0xf000c, 0x2050);
  39         write32(mmio + 0x60100, 0x44000);
  40         write32(mmio + 0xf000c, 0x22050);
  41
  42         mdelay(1);
  43
  44         write32(mmio + 0x000f0018, 0x0000008ff);
  45         write32(mmio + 0x000f1018, 0x0000008ff);
  46
  47         write32(mmio + 0x000f000c, 0x001a2050);
  48         write32(mmio + 0x00060100, 0x001c4000);
  49
  50         write32(mmio + 0x00060100, 0x801c4000);
  51         write32(mmio + 0x000f000c, 0x801a2050);
  52
  53         write32(mmio + 0x00060100, 0x801c4000);
  54         write32(mmio + 0x000f000c, 0x801a2050);
  55         mdelay(1);
  56
  57         read32(mmio + 0x000f0014); // = 0x00000100
  58         write32(mmio + 0x000f0014, 0x00000100);
  59         write32(mmio + 0x00060100, 0x901c4000);
  60         write32(mmio + 0x000f000c, 0x801a2150);
  61         mdelay(1);
  62         read32(mmio + 0x000f0014); // = 0x00000600
  63 }
  64
  65 static void power_port(u8 *mmio)
  66 {
  67         read32(mmio + 0x000e1100); // = 0x00000000
  68         write32(mmio + 0x000e1100, 0x00000000);
  69         write32(mmio + 0x000e1100, 0x00010000);
  70         read32(mmio + 0x000e1100); // = 0x00010000
  71         read32(mmio + 0x000e1100); // = 0x00010000
  72         read32(mmio + 0x000e1100); // = 0x00000000
  73         write32(mmio + 0x000e1100, 0x00000000);
  74         read32(mmio + 0x000e1100); // = 0x00000000
  75         read32(mmio + 0x000e4200); // = 0x0000001c
  76         write32(mmio + 0x000e4210, 0x8004003e);
  77         write32(mmio + 0x000e4214, 0x80060002);
  78         write32(mmio + 0x000e4218, 0x01000000);
  79         read32(mmio + 0x000e4210); // = 0x5144003e
  80         write32(mmio + 0x000e4210, 0x5344003e);
  81         read32(mmio + 0x000e4210); // = 0x0144003e
  82         write32(mmio + 0x000e4210, 0x8074003e);
  83         read32(mmio + 0x000e4210); // = 0x5144003e
  84         read32(mmio + 0x000e4210); // = 0x5144003e
  85         write32(mmio + 0x000e4210, 0x5344003e);
  86         read32(mmio + 0x000e4210); // = 0x0144003e
  87         write32(mmio + 0x000e4210, 0x8074003e);
  88         read32(mmio + 0x000e4210); // = 0x5144003e
  89         read32(mmio + 0x000e4210); // = 0x5144003e
  90         write32(mmio + 0x000e4210, 0x5344003e);
  91         read32(mmio + 0x000e4210); // = 0x0144003e
  92         write32(mmio + 0x000e4210, 0x8074003e);
  93         read32(mmio + 0x000e4210); // = 0x5144003e
  94         read32(mmio + 0x000e4210); // = 0x5144003e
  95         write32(mmio + 0x000e4210, 0x5344003e);
  96         write32(mmio + 0x000e4f00, 0x0100030c);
  97         write32(mmio + 0x000e4f04, 0x00b8230c);
  98         write32(mmio + 0x000e4f08, 0x06f8930c);
  99         write32(mmio + 0x000e4f0c, 0x09f8e38e);
 100         write32(mmio + 0x000e4f10, 0x00b8030c);
 101         write32(mmio + 0x000e4f14, 0x0b78830c);
 102         write32(mmio + 0x000e4f18, 0x0ff8d3cf);
 103         write32(mmio + 0x000e4f1c, 0x01e8030c);
 104         write32(mmio + 0x000e4f20, 0x0ff863cf);
 105         write32(mmio + 0x000e4f24, 0x0ff803cf);
 106         write32(mmio + 0x000c4030, 0x00001000);
 107         read32(mmio + 0x000c4000); // = 0x00000000
 108         write32(mmio + 0x000c4030, 0x00001000);
 109         read32(mmio + 0x000e1150); // = 0x0000001c
 110         write32(mmio + 0x000e1150, 0x0000089c);
 111         write32(mmio + 0x000fcc00, 0x01986f00);
 112         write32(mmio + 0x000fcc0c, 0x01986f00);
 113         write32(mmio + 0x000fcc18, 0x01986f00);
 114         write32(mmio + 0x000fcc24, 0x01986f00);
 115         read32(mmio + 0x000c4000); // = 0x00000000
 116         read32(mmio + 0x000e1180); // = 0x40000002
 117 }
 118
 119 int i915lightup_sandy(const struct i915_gpu_controller_info *info,
 120                 u32 physbase, u16 piobase, u8 *mmio, u32 lfb)
 121 {
 122         int i;
 123         u8 edid_data[128];
 124         struct edid edid;
 125         struct edid_mode *mode;
 126         u32 hactive, vactive, right_border, bottom_border;
 127         int hpolarity, vpolarity;
 128         u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
 129         u32 candp1, candn;
 130         u32 best_delta = 0xffffffff;
 131         u32 target_frequency;
 132         u32 pixel_p1 = 1;
 133         u32 pixel_n = 1;
 134         u32 pixel_m1 = 1;
 135         u32 pixel_m2 = 1;
 136         u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000;
 137         u32 data_m1;
 138         u32 data_n1 = 0x00800000;
 139         u32 link_m1;
 140         u32 link_n1 = 0x00080000;
 141
 142         if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT))
 143                 return 0;
 144
 145         write32(mmio + 0x00070080, 0x00000000);
 146         write32(mmio + DSPCNTR(0), 0x00000000);
 147         write32(mmio + 0x00071180, 0x00000000);
 148         write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE);
 149         write32(mmio + 0x0007019c, 0x00000000);
 150         write32(mmio + 0x0007119c, 0x00000000);
 151         write32(mmio + 0x000ec008, 0x2c010000);
 152         write32(mmio + 0x000ec020, 0x2c010000);
 153         write32(mmio + 0x000ec038, 0x2c010000);
 154         write32(mmio + 0x000ec050, 0x2c010000);
 155         write32(mmio + 0x000ec408, 0x2c010000);
 156         write32(mmio + 0x000ec420, 0x2c010000);
 157         write32(mmio + 0x000ec438, 0x2c010000);
 158         write32(mmio + 0x000ec450, 0x2c010000);
 159         vga_gr_write(0x18, 0);
 160         write32(mmio + 0x00042004, 0x02000000);
 161         write32(mmio + 0x000fd034, 0x8421ffe0);
 162
 163         /* Setup GTT.  */
 164         for (i = 0; i < 0x2000; i++)
 165         {
 166                 outl((i << 2) | 1, piobase);
 167                 outl(physbase + (i << 12) + 1, piobase + 4);
 168         }
 169
 170         vga_misc_write(0x67);
 171
 172         const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
 173                     0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
 174                     0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
 175                     0xff
 176         };
 177         vga_cr_write(0x11, 0);
 178
 179         for (i = 0; i <= 0x18; i++)
 180                 vga_cr_write(i, cr[i]);
 181
 182         power_port(mmio);
 183
 184         intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128);
 185         decode_edid(edid_data, sizeof(edid_data), &edid);
 186         mode = &edid.mode;
 187
 188         /* Disable screen memory to prevent garbage from appearing.  */
 189         vga_sr_write(1, vga_sr_read(1) | 0x20);
 190
 191         hactive = edid.x_resolution;
 192         vactive = edid.y_resolution;
 193         right_border = mode->hborder;
 194         bottom_border = mode->vborder;
 195         hpolarity = (mode->phsync == '-');
 196         vpolarity = (mode->pvsync == '-');
 197         vsync = mode->vspw;
 198         hsync = mode->hspw;
 199         vblank = mode->vbl;
 200         hblank = mode->hbl;
 201         hfront_porch = mode->hso;
 202         vfront_porch = mode->vso;
 203
 204         target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
 205                 : (2 * mode->pixel_clock);
 206
 207         if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
 208                 vga_sr_write(1, 1);
 209                 vga_sr_write(0x2, 0xf);
 210                 vga_sr_write(0x3, 0x0);
 211                 vga_sr_write(0x4, 0xe);
 212                 vga_gr_write(0, 0x0);
 213                 vga_gr_write(1, 0x0);
 214                 vga_gr_write(2, 0x0);
 215                 vga_gr_write(3, 0x0);
 216                 vga_gr_write(4, 0x0);
 217                 vga_gr_write(5, 0x0);
 218                 vga_gr_write(6, 0x5);
 219                 vga_gr_write(7, 0xf);
 220                 vga_gr_write(0x10, 0x1);
 221                 vga_gr_write(0x11, 0);
 222
 223                 edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
 224
 225                 write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
 226                 write32(mmio + DSPADDR(0), 0);
 227                 write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
 228                 write32(mmio + DSPSURF(0), 0);
 229                 for (i = 0; i < 0x100; i++)
 230                         write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
 231         } else {
 232                 vga_textmode_init();
 233         }
 234
 235         /* Find suitable divisors.  */
 236         for (candp1 = 1; candp1 <= 8; candp1++) {
 237                 for (candn = 5; candn <= 10; candn++) {
 238                         u32 cur_frequency;
 239                         u32 m; /* 77 - 131.  */
 240                         u32 denom; /* 35 - 560.  */
 241                         u32 current_delta;
 242
 243                         denom = candn * candp1 * 7;
 244                         /* Doesnt overflow for up to
 245                            5000000 kHz = 5 GHz.  */
 246                         m = (target_frequency * denom + 60000) / 120000;
 247
 248                         if (m < 77 || m > 131)
 249                                 continue;
 250
 251                         cur_frequency = (120000 * m) / denom;
 252                         if (target_frequency > cur_frequency)
 253                                 current_delta = target_frequency - cur_frequency;
 254                         else
 255                                 current_delta = cur_frequency - target_frequency;
 256
 257
 258                         if (best_delta > current_delta) {
 259                                 best_delta = current_delta;
 260                                 pixel_n = candn;
 261                                 pixel_p1 = candp1;
 262                                 pixel_m2 = ((m + 3) % 5) + 7;
 263                                 pixel_m1 = (m - pixel_m2) / 5;
 264                         }
 265                 }
 266         }
 267
 268         if (best_delta == 0xffffffff) {
 269                 printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
 270                 return 0;
 271         }
 272
 273         link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
 274         data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
 275                 / (link_frequency * 8 * 4);
 276
 277         printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
 278                hactive, vactive);
 279         printk(BIOS_DEBUG, "Borders %d x %d\n",
 280                right_border, bottom_border);
 281         printk(BIOS_DEBUG, "Blank %d x %d\n",
 282                hblank, vblank);
 283         printk(BIOS_DEBUG, "Sync %d x %d\n",
 284                hsync, vsync);
 285         printk(BIOS_DEBUG, "Front porch %d x %d\n",
 286                hfront_porch, vfront_porch);
 287         printk(BIOS_DEBUG, (info->use_spread_spectrum_clock
 288                             ? "Spread spectrum clock\n" : "DREF clock\n"));
 289         printk(BIOS_DEBUG,
 290                mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
 291         printk(BIOS_DEBUG, "Polarities %d, %d\n",
 292                hpolarity, vpolarity);
 293         printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
 294                data_m1, data_n1);
 295         printk(BIOS_DEBUG, "Link frequency %d kHz\n",
 296                link_frequency);
 297         printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n",
 298                link_m1, link_n1);
 299         printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
 300                pixel_n, pixel_m1, pixel_m2, pixel_p1);
 301         printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
 302                120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
 303                / (pixel_p1 * 7));
 304
 305         write32(mmio + PCH_LVDS,
 306                 (hpolarity << 20) | (vpolarity << 21)
 307                 | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 308                    | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 309                 | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 310                 | LVDS_DETECTED);
 311         write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
 312         write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock
 313                                           ? 0x1002 : 0x400));
 314         mdelay(1);
 315         write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
 316                 | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
 317         write32(mmio + _PCH_FP0(0),
 318                 ((pixel_n - 2) << 16)
 319                 | ((pixel_m1 - 2) << 8) | pixel_m2);
 320         write32(mmio + PCH_DPLL_SEL, 8);
 321         write32(mmio + _PCH_DPLL(0),
 322                 DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
 323                 | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
 324                    : DPLLB_LVDS_P2_CLOCK_DIV_14)
 325                 | (0x10000 << (pixel_p1 - 1))
 326                 | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
 327                 | (0x1 << (pixel_p1 - 1)));
 328         mdelay(1);
 329         write32(mmio + _PCH_DPLL(0),
 330                 DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
 331                 | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
 332                    : DPLLB_LVDS_P2_CLOCK_DIV_14)
 333                 | (0x10000 << (pixel_p1 - 1))
 334                 | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
 335                 | (0x1 << (pixel_p1 - 1)));
 336         /* Re-lock the registers.  */
 337         write32(mmio + PCH_PP_CONTROL,
 338                 (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
 339
 340         write32(mmio + PCH_LVDS,
 341                 (hpolarity << 20) | (vpolarity << 21)
 342                 | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 343                    | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 344                 | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 345                 | LVDS_DETECTED);
 346
 347         write32(mmio + HTOTAL(0),
 348                 ((hactive + right_border + hblank - 1) << 16)
 349                 | (hactive - 1));
 350         write32(mmio + HBLANK(0),
 351                 ((hactive + right_border + hblank - 1) << 16)
 352                 | (hactive + right_border - 1));
 353         write32(mmio + HSYNC(0),
 354                 ((hactive + right_border + hfront_porch + hsync - 1) << 16)
 355                 | (hactive + right_border + hfront_porch - 1));
 356
 357         write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
 358                 | (vactive - 1));
 359         write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
 360                 | (vactive + bottom_border - 1));
 361         write32(mmio + VSYNC(0),
 362                 (vactive + bottom_border + vfront_porch + vsync - 1)
 363                 | (vactive + bottom_border + vfront_porch - 1));
 364
 365         write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
 366
 367         write32(mmio + PF_WIN_POS(0), 0);
 368         if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
 369                 write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
 370                 write32(mmio + PF_CTL(0),0);
 371                 write32(mmio + PF_WIN_SZ(0), 0);
 372         } else {
 373                 write32(mmio + PIPESRC(0), (639 << 16) | 399);
 374                 write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
 375                 write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
 376         }
 377
 378         mdelay(1);
 379
 380         write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
 381         write32(mmio + PIPE_DATA_N1(0), data_n1);
 382         write32(mmio + PIPE_LINK_M1(0), link_m1);
 383         write32(mmio + PIPE_LINK_N1(0), link_n1);
 384
 385         write32(mmio + 0x000f000c, 0x00002040);
 386         mdelay(1);
 387         write32(mmio + 0x000f000c, 0x00002050);
 388         write32(mmio + 0x00060100, 0x00044000);
 389         mdelay(1);
 390         write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
 391         write32(mmio + 0x000f000c, 0x00022050);
 392         write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
 393         write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
 394
 395         if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
 396                 write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
 397         else
 398                 write32(mmio + CPU_VGACNTRL, 0x20298e);
 399
 400         train_link(mmio);
 401
 402         if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
 403                 write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
 404                 mdelay(1);
 405         }
 406
 407         write32(mmio + TRANS_HTOTAL(0),
 408                 ((hactive + right_border + hblank - 1) << 16)
 409                 | (hactive - 1));
 410         write32(mmio + TRANS_HBLANK(0),
 411                 ((hactive + right_border + hblank - 1) << 16)
 412                 | (hactive + right_border - 1));
 413         write32(mmio + TRANS_HSYNC(0),
 414                 ((hactive + right_border + hfront_porch + hsync - 1) << 16)
 415                 | (hactive + right_border + hfront_porch - 1));
 416
 417         write32(mmio + TRANS_VTOTAL(0),
 418                 ((vactive + bottom_border + vblank - 1) << 16)
 419                 | (vactive - 1));
 420         write32(mmio + TRANS_VBLANK(0),
 421                 ((vactive + bottom_border + vblank - 1) << 16)
 422                 | (vactive + bottom_border - 1));
 423         write32(mmio + TRANS_VSYNC(0),
 424                 (vactive + bottom_border + vfront_porch + vsync - 1)
 425                 | (vactive + bottom_border + vfront_porch - 1));
 426
 427         write32(mmio + 0x00060100, 0xb01c4000);
 428         write32(mmio + 0x000f000c, 0x801a2350);
 429         mdelay(1);
 430
 431         if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE))
 432                 write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
 433                                            | TRANS_STATE_MASK);
 434         else
 435                 write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC);
 436
 437         write32(mmio + PCH_LVDS,
 438                 LVDS_PORT_ENABLE
 439                 | (hpolarity << 20) | (vpolarity << 21)
 440                 | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 441                    | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 442                 | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 443                 | LVDS_DETECTED);
 444
 445         write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 446         write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
 447         mdelay(1);
 448         write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
 449                 | PANEL_POWER_ON | PANEL_POWER_RESET);
 450
 451         printk (BIOS_DEBUG, "waiting for panel powerup\n");
 452         while (1) {
 453                 u32 reg32;
 454                 reg32 = read32(mmio + PCH_PP_STATUS);
 455                 if (((reg32 >> 28) & 3) == 0)
 456                         break;
 457         }
 458         printk (BIOS_DEBUG, "panel powered up\n");
 459
 460         write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
 461
 462         /* Enable screen memory.  */
 463         vga_sr_write(1, vga_sr_read(1) & ~0x20);
 464
 465         /* Clear interrupts. */
 466         write32(mmio + DEIIR, 0xffffffff);
 467         write32(mmio + SDEIIR, 0xffffffff);
 468
 469         if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
 470                 memset ((void *) lfb, 0, edid.x_resolution
 471                                         * edid.y_resolution * 4);
 472                 set_vbe_mode_info_valid(&edid, lfb);
 473         }
 474
 475         /* Linux relies on VBT for panel info.  */
 476         generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)),
 477                                   "$VBT SNB/IVB-MOBILE ");
 478
 479         return 1;
 480 }