src/northbridge/intel/sandybridge/acpi.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  * Copyright (C) 2012 The Chromium OS Authors
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; version 2 of
  10  * the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <types.h>
  19 #include <string.h>
  20 #include <console/console.h>
  21 #include <arch/io.h>
  22 #include <arch/acpi.h>
  23 #include <device/device.h>
  24 #include <device/pci.h>
  25 #include <device/pci_ids.h>
  26 #include <drivers/intel/gma/i915.h>
  27 #include <arch/acpigen.h>
  28 #include "sandybridge.h"
  29 #include <cbmem.h>
  30 #include <drivers/intel/gma/intel_bios.h>
  31
  32 unsigned long acpi_fill_mcfg(unsigned long current)
  33 {
  34         device_t dev;
  35         u32 pciexbar = 0;
  36         u32 pciexbar_reg;
  37         int max_buses;
  38
  39         dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SB, 0);
  40         if (!dev)
  41                 dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_IB, 0);
  42         if (!dev)
  43                 return current;
  44
  45         pciexbar_reg=pci_read_config32(dev, PCIEXBAR);
  46
  47         // MMCFG not supported or not enabled.
  48         if (!(pciexbar_reg & (1 << 0)))
  49                 return current;
  50
  51         switch ((pciexbar_reg >> 1) & 3) {
  52         case 0: // 256MB
  53                 pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
  54                 max_buses = 256;
  55                 break;
  56         case 1: // 128M
  57                 pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
  58                 max_buses = 128;
  59                 break;
  60         case 2: // 64M
  61                 pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
  62                 max_buses = 64;
  63                 break;
  64         default: // RSVD
  65                 return current;
  66         }
  67
  68         if (!pciexbar)
  69                 return current;
  70
  71         current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
  72                         pciexbar, 0x0, 0x0, max_buses - 1);
  73
  74         return current;
  75 }
  76
  77 static void *get_intel_vbios(void)
  78 {
  79         /* This should probably be looking at CBFS or we should always
  80          * deploy the VBIOS on Intel systems, even if we don't run it
  81          * in coreboot (e.g. SeaBIOS only scenarios).
  82          */
  83         u8 *vbios = (u8 *)0xc0000;
  84
  85         optionrom_header_t *oprom = (optionrom_header_t *)vbios;
  86         optionrom_pcir_t *pcir = (optionrom_pcir_t *)(vbios +
  87                                                 oprom->pcir_offset);
  88
  89
  90         printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
  91                 oprom->signature, pcir->vendor, pcir->classcode[0],
  92                 pcir->classcode[1], pcir->classcode[2]);
  93
  94
  95         if ((oprom->signature == OPROM_SIGNATURE) &&
  96                 (pcir->vendor == PCI_VENDOR_ID_INTEL) &&
  97                 (pcir->classcode[0] == 0x00) &&
  98                 (pcir->classcode[1] == 0x00) &&
  99                 (pcir->classcode[2] == 0x03))
 100                 return (void *)vbios;
 101
 102         return NULL;
 103 }
 104
 105 static int init_opregion_vbt(igd_opregion_t *opregion)
 106 {
 107         void *vbios;
 108         vbios = get_intel_vbios();
 109         if (!vbios) {
 110                 printk(BIOS_DEBUG, "VBIOS not found.\n");
 111                 return 1;
 112         }
 113
 114         printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
 115         optionrom_header_t *oprom = (optionrom_header_t *)vbios;
 116         optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
 117                                                 oprom->vbt_offset);
 118
 119         if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
 120                 printk(BIOS_DEBUG, "VBT not found!\n");
 121                 return 1;
 122         }
 123
 124         memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
 125         memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
 126                                                 vbt->hdr_vbt_size : 7168);
 127
 128         return 0;
 129 }
 130
 131
 132 /* Initialize IGD OpRegion, called from ACPI code */
 133 int init_igd_opregion(igd_opregion_t *opregion)
 134 {
 135         device_t igd;
 136         u16 reg16;
 137
 138         memset((void *)opregion, 0, sizeof(igd_opregion_t));
 139
 140         // FIXME if IGD is disabled, we should exit here.
 141
 142         memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
 143                 sizeof(opregion->header.signature));
 144
 145         /* 8kb */
 146         opregion->header.size = sizeof(igd_opregion_t) / 1024;
 147         opregion->header.version = IGD_OPREGION_VERSION;
 148
 149         // FIXME We just assume we're mobile for now
 150         opregion->header.mailboxes = MAILBOXES_MOBILE;
 151
 152         // TODO Initialize Mailbox 1
 153
 154         // TODO Initialize Mailbox 3
 155         opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
 156         opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
 157         opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
 158         opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
 159         opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
 160         opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
 161         opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
 162         opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
 163         opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
 164         opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
 165         opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
 166         opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
 167         opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
 168         opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
 169         opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
 170
 171         init_opregion_vbt(opregion);
 172
 173         /* TODO This needs to happen in S3 resume, too.
 174          * Maybe it should move to the finalize handler
 175          */
 176         igd = dev_find_slot(0, PCI_DEVFN(0x2, 0));
 177
 178         pci_write_config32(igd, ASLS, (u32)opregion);
 179         reg16 = pci_read_config16(igd, SWSCI);
 180         reg16 &= ~(1 << 0);
 181         reg16 |= (1 << 15);
 182         pci_write_config16(igd, SWSCI, reg16);
 183
 184         /* clear dmisci status */
 185         reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
 186         reg16 |= DMISCI_STS; // reference code does an &=
 187         outw(DEFAULT_PMBASE + TCO1_STS, reg16);
 188
 189         /* clear acpi tco status */
 190         outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
 191
 192         /* enable acpi tco scis */
 193         reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
 194         reg16 |= TCOSCI_EN;
 195         outw(DEFAULT_PMBASE + GPE0_EN, reg16);
 196
 197         return 0;
 198 }
 199
 200 void *igd_make_opregion(void)
 201 {
 202         igd_opregion_t *opregion;
 203
 204         printk(BIOS_DEBUG, "ACPI:    * IGD OpRegion\n");
 205         opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof (*opregion));
 206         if (opregion)
 207                 init_igd_opregion(opregion);
 208         return opregion;
 209 }