2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2010 coresystems GmbH
5 * Copyright (C) 2011 Google Inc
6 * Copyright (C) 2013 Vladimir Serbinenko
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
20 #include <console/console.h>
22 #include <device/pci_def.h>
24 #include <cpu/x86/msr.h>
25 #include <cpu/intel/speedstep.h>
26 #include <cpu/intel/turbo.h>
31 static void nehalem_setup_bars(void)
33 /* Setting up Southbridge. In the northbridge code. */
34 printk(BIOS_DEBUG
, "Setting up static southbridge registers...");
35 pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA
, (uintptr_t)DEFAULT_RCBA
| 1);
37 pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE
, DEFAULT_PMBASE
| 1);
39 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80);
41 printk(BIOS_DEBUG
, " done.\n");
43 printk(BIOS_DEBUG
, "Disabling Watchdog reboot...");
45 RCBA32(GCS
) = RCBA32(GCS
) | (1 << 5);
47 outw((1 << 11), DEFAULT_PMBASE
| 0x60 | 0x08);
49 outw(inw(DEFAULT_PMBASE
| 0x60 | 0x06) | 2,
50 DEFAULT_PMBASE
| 0x60 | 0x06);
51 printk(BIOS_DEBUG
, " done.\n");
53 printk(BIOS_DEBUG
, "Setting up static northbridge registers...");
54 /* Set up all hardcoded northbridge BARs */
55 pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR
, DEFAULT_EPBAR
| 1);
56 pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR
+ 4,
57 (0LL + DEFAULT_EPBAR
) >> 32);
58 pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR
, (uintptr_t)DEFAULT_MCHBAR
| 1);
59 pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR
+ 4,
60 (0LL + (uintptr_t)DEFAULT_MCHBAR
) >> 32);
62 pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR
, (uintptr_t)DEFAULT_DMIBAR
| 1);
63 pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR
+ 4,
64 (0LL + (uintptr_t)DEFAULT_DMIBAR
) >> 32);
66 /* Set C0000-FFFFF to access RAM on both reads and writes */
67 pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30);
68 pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(1), 0x33);
69 pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(2), 0x33);
70 pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(3), 0x33);
71 pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(4), 0x33);
72 pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33);
73 pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33);
75 #if CONFIG_ELOG_BOOT_COUNT
76 /* Increment Boot Counter for non-S3 resume */
77 if ((inw(DEFAULT_PMBASE
+ PM1_STS
) & WAK_STS
) &&
78 ((inl(DEFAULT_PMBASE
+ PM1_CNT
) >> 10) & 7) != SLP_TYP_S3
)
79 boot_count_increment();
82 printk(BIOS_DEBUG
, " done.\n");
84 #if CONFIG_ELOG_BOOT_COUNT
85 /* Increment Boot Counter except when resuming from S3 */
86 if ((inw(DEFAULT_PMBASE
+ PM1_STS
) & WAK_STS
) &&
87 ((inl(DEFAULT_PMBASE
+ PM1_CNT
) >> 10) & 7) == SLP_TYP_S3
)
89 boot_count_increment();
93 static void early_cpu_init (void)
97 /* bit 0 = disable multicore,
98 bit 1 = disable quadcore,
99 bit 8 = disable hyperthreading. */
100 pci_write_config32(PCI_DEV(0xff, 0x00, 0), 0x80,
101 (pci_read_config32(PCI_DEV(0xff, 0x0, 0x0), 0x80) & 0xfffffefc) | 0x10000);
104 struct cpuid_result result
;
105 result
= cpuid_ext(0x6, 0x8b);
106 if (!(result
.eax
& 0x2)) {
107 m
= rdmsr(MSR_FSB_CLOCK_VCC
);
108 reg8
= ((m
.lo
& 0xff00) >> 8) + 1;
109 m
= rdmsr (IA32_PERF_CTL
);
110 m
.lo
= (m
.lo
& ~0xff) | reg8
;
111 wrmsr(IA32_PERF_CTL
, m
);
113 m
= rdmsr(MSR_IA32_MISC_ENABLES
);
117 wrmsr(MSR_IA32_MISC_ENABLES
, m
);
120 m
= rdmsr(MSR_FSB_CLOCK_VCC
);
121 reg8
= ((m
.lo
& 0xff00) >> 8) + 1;
123 m
= rdmsr (IA32_PERF_CTL
);
124 m
.lo
= (m
.lo
& ~0xff) | reg8
;
125 wrmsr(IA32_PERF_CTL
, m
);
127 m
= rdmsr(MSR_IA32_MISC_ENABLES
);
129 wrmsr(MSR_IA32_MISC_ENABLES
, m
);
132 void nehalem_early_initialization(int chipset_type
)
137 /* Device ID Override Enable should be done very early */
138 capid0_a
= pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
139 if (capid0_a
& (1 << 10)) {
140 reg8
= pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
141 reg8
&= ~7; /* Clear 2:0 */
143 if (chipset_type
== NEHALEM_MOBILE
)
144 reg8
|= 1; /* Set bit 0 */
146 pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8
);
149 /* Setup all BARs required for early PCIe and raminit */
150 nehalem_setup_bars();
153 pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN
, 9 | 2);
157 pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR
);
158 pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND
,
159 PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
);
161 /* Magic for S3 resume. Must be done early. */
162 if (((inl(DEFAULT_PMBASE
+ PM1_CNT
) >> 10) & 7) == SLP_TYP_S3
) {
163 MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6;
164 MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4;