2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include "../nehalem.h"
18 #include "hostbridge.asl"
20 /* PCI Device Resource Consumption */
23 Name (_HID, EISAID("PNP0C02"))
26 Name (PDRS, ResourceTemplate() {
27 Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
28 Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000)
29 Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
30 Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
31 Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
32 Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
33 Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
34 Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
36 #if CONFIG_CHROMEOS_RAMOOPS
37 Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
38 CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
41 /* Required for SandyBridge sighting 3715511 */
42 Memory32Fixed(ReadWrite, 0x20000000, 0x00200000)
43 Memory32Fixed(ReadWrite, 0x40000000, 0x00200000)
46 // Current Resource Settings
47 Method (_CRS, 0, Serialized)
53 // Integrated graphics 0:2.0
54 #include <drivers/intel/gma/acpi/pch.asl>