src/northbridge/intel/i945/ram_calc.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 // Use simple device model for this file even in ramstage
  17 #define __SIMPLE_DEVICE__
  18
  19 #include <arch/io.h>
  20 #include <cbmem.h>
  21 #include "i945.h"
  22
  23 static uintptr_t smm_region_start(void)
  24 {
  25         uintptr_t tom;
  26
  27         if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
  28                 /* IGD enabled, get top of Memory from BSM register */
  29                 tom = pci_read_config32(PCI_DEV(0,2,0), BSM);
  30         } else {
  31                 tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
  32         }
  33
  34         /* if TSEG enabled subtract size */
  35         switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {
  36         case 0x01:
  37                 /* 1MB TSEG */
  38                 tom -= 0x100000;
  39                 break;
  40         case 0x03:
  41                 /* 2MB TSEG */
  42                 tom -= 0x200000;
  43                 break;
  44         case 0x05:
  45                 /* 8MB TSEG */
  46                 tom -= 0x800000;
  47                 break;
  48         default:
  49                 /* TSEG either disabled or invalid */
  50                 break;
  51         }
  52         return tom;
  53 }
  54
  55 void *cbmem_top(void)
  56 {
  57         return (void *) smm_region_start();
  58 }