src/northbridge/intel/i945/early_init.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2010 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <stdint.h>
  17 #include <stdlib.h>
  18 #include <console/console.h>
  19 #include <arch/io.h>
  20 #include <device/pci_def.h>
  21 #include <cbmem.h>
  22 #include <halt.h>
  23 #include <string.h>
  24 #include "i945.h"
  25
  26 int i945_silicon_revision(void)
  27 {
  28         return pci_read_config8(PCI_DEV(0, 0x00, 0), PCI_CLASS_REVISION);
  29 }
  30
  31 static void i945m_detect_chipset(void)
  32 {
  33         u8 reg8;
  34
  35         printk(BIOS_INFO, "\n");
  36         reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4;
  37         switch (reg8) {
  38         case 1:
  39                 printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express");
  40                 break;
  41         case 2:
  42                 printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU/GSE Express");
  43                 break;
  44         case 3:
  45                 printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express");
  46                 break;
  47         case 5:
  48                 printk(BIOS_INFO, "Intel(R) 82945GT Express");
  49                 break;
  50         case 6:
  51                 printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express");
  52                 break;
  53         default:
  54                 printk(BIOS_INFO, "Unknown (%02x)", reg8);      /* Others reserved. */
  55         }
  56         printk(BIOS_INFO, " Chipset\n");
  57
  58         printk(BIOS_DEBUG, "(G)MCH capable of up to FSB ");
  59         reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5;
  60         switch (reg8) {
  61         case 2:
  62                 printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */
  63                 break;
  64         case 3:
  65                 printk(BIOS_DEBUG, "667 MHz");
  66                 break;
  67         case 4:
  68                 printk(BIOS_DEBUG, "533 MHz");
  69                 break;
  70         default:
  71                 printk(BIOS_DEBUG, "N/A MHz (%02x)", reg8);
  72         }
  73         printk(BIOS_DEBUG, "\n");
  74
  75         printk(BIOS_DEBUG, "(G)MCH capable of ");
  76         reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07);
  77         switch (reg8) {
  78         case 2:
  79                 printk(BIOS_DEBUG, "up to DDR2-667");
  80                 break;
  81         case 3:
  82                 printk(BIOS_DEBUG, "up to DDR2-533");
  83                 break;
  84         case 4:
  85                 printk(BIOS_DEBUG, "DDR2-400");
  86                 break;
  87         default:
  88                 printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);      /* Others reserved. */
  89         }
  90         printk(BIOS_DEBUG, "\n");
  91 #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
  92         printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
  93 #endif
  94 }
  95
  96 static void i945_detect_chipset(void)
  97 {
  98         u8 reg8;
  99
 100         printk(BIOS_INFO, "\nIntel(R) ");
 101
 102         reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3);
 103         switch (reg8) {
 104         case 0:
 105         case 1:
 106                 printk(BIOS_INFO, "82945G");
 107                 break;
 108         case 2:
 109         case 3:
 110                 printk(BIOS_INFO, "82945P");
 111                 break;
 112         case 4:
 113                 printk(BIOS_INFO, "82945GC");
 114                 break;
 115         case 5:
 116                 printk(BIOS_INFO, "82945GZ");
 117                 break;
 118         case 6:
 119         case 7:
 120                 printk(BIOS_INFO, "82945PL");
 121                 break;
 122         default:
 123                 break;
 124         }
 125         printk(BIOS_INFO, " Chipset\n");
 126
 127         printk(BIOS_DEBUG, "(G)MCH capable of ");
 128         reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07);
 129         switch (reg8) {
 130         case 0:
 131                 printk(BIOS_DEBUG, "up to DDR2-667");
 132                 break;
 133         case 3:
 134                 printk(BIOS_DEBUG, "up to DDR2-533");
 135                 break;
 136         default:
 137                 printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);      /* Others reserved. */
 138         }
 139         printk(BIOS_DEBUG, "\n");
 140 #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
 141         printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
 142 #endif
 143 }
 144
 145 static void i945_setup_bars(void)
 146 {
 147         u8 reg8;
 148
 149         /* As of now, we don't have all the A0 workarounds implemented */
 150         if (i945_silicon_revision() == 0)
 151                 printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n");
 152
 153         /* Setting up Southbridge. In the northbridge code. */
 154         printk(BIOS_DEBUG, "Setting up static southbridge registers...");
 155         pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
 156
 157         pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
 158         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
 159
 160         pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
 161         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10);   /* Enable GPIOs */
 162         setup_ich7_gpios();
 163         printk(BIOS_DEBUG, " done.\n");
 164
 165         printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
 166         RCBA32(GCS) = RCBA32(GCS) | (1 << 5);   /* No reset */
 167         outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);  /* halt timer */
 168         printk(BIOS_DEBUG, " done.\n");
 169
 170         /* Enable upper 128bytes of CMOS */
 171         RCBA32(0x3400) = (1 << 2);
 172
 173         printk(BIOS_DEBUG, "Setting up static northbridge registers...");
 174         /* Set up all hardcoded northbridge BARs */
 175         pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
 176         pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
 177         pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
 178         pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);
 179
 180         /* Hardware default is 8MB UMA. If someone wants to make this a
 181          * CMOS or compile time option, send a patch.
 182          * pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x30);
 183          */
 184
 185         /* Set C0000-FFFFF to access RAM on both reads and writes */
 186         pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
 187         pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);
 188         pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33);
 189         pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33);
 190         pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33);
 191         pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
 192         pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
 193
 194         pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC);
 195         printk(BIOS_DEBUG, " done.\n");
 196
 197         /* Wait for MCH BAR to come up */
 198         printk(BIOS_DEBUG, "Waiting for MCHBAR to come up...");
 199         if ((pci_read_config32(PCI_DEV(0, 0x00, 0), 0xe4) & 0x20000) == 0x00) { /* Bit 49 of CAPID0 */
 200                 do {
 201                         reg8 = *(volatile u8 *)0xfed40000;
 202                 } while (!(reg8 & 0x80));
 203         }
 204         printk(BIOS_DEBUG, "ok\n");
 205 }
 206
 207 static void i945_setup_egress_port(void)
 208 {
 209         u32 reg32;
 210         u32 timeout;
 211
 212         printk(BIOS_DEBUG, "Setting up Egress Port RCRB\n");
 213
 214         /* Egress Port Virtual Channel 0 Configuration */
 215
 216         /* map only TC0 to VC0 */
 217         reg32 = EPBAR32(EPVC0RCTL);
 218         reg32 &= 0xffffff01;
 219         EPBAR32(EPVC0RCTL) = reg32;
 220
 221         reg32 = EPBAR32(EPPVCCAP1);
 222         reg32 &= ~(7 << 0);
 223         reg32 |= 1;
 224         EPBAR32(EPPVCCAP1) = reg32;
 225
 226         /* Egress Port Virtual Channel 1 Configuration */
 227         reg32 = EPBAR32(0x2c);
 228         reg32 &= 0xffffff00;
 229         if ((MCHBAR32(CLKCFG) & 7) == 1)
 230                 reg32 |= 0x0d;  /* 533MHz */
 231         if ((MCHBAR32(CLKCFG) & 7) == 3)
 232                 reg32 |= 0x10;  /* 667MHz */
 233         EPBAR32(0x2c) = reg32;
 234
 235         EPBAR32(EPVC1MTS) = 0x0a0a0a0a;
 236
 237         reg32 = EPBAR32(EPVC1RCAP);
 238         reg32 &= ~(0x7f << 16);
 239         reg32 |= (0x0a << 16);
 240         EPBAR32(EPVC1RCAP) = reg32;
 241
 242         if ((MCHBAR32(CLKCFG) & 7) == 1) {      /* 533MHz */
 243                 EPBAR32(EPVC1IST + 0) = 0x009c009c;
 244                 EPBAR32(EPVC1IST + 4) = 0x009c009c;
 245         }
 246
 247         if ((MCHBAR32(CLKCFG) & 7) == 3) {      /* 667MHz */
 248                 EPBAR32(EPVC1IST + 0) = 0x00c000c0;
 249                 EPBAR32(EPVC1IST + 4) = 0x00c000c0;
 250         }
 251
 252         /* Is internal graphics enabled? */
 253         if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
 254                 MCHBAR32(MMARB1) |= (1 << 17);
 255         }
 256
 257         /* Assign Virtual Channel ID 1 to VC1 */
 258         reg32 = EPBAR32(EPVC1RCTL);
 259         reg32 &= ~(7 << 24);
 260         reg32 |= (1 << 24);
 261         EPBAR32(EPVC1RCTL) = reg32;
 262
 263         reg32 = EPBAR32(EPVC1RCTL);
 264         reg32 &= 0xffffff01;
 265         reg32 |= (1 << 7);
 266         EPBAR32(EPVC1RCTL) = reg32;
 267
 268         EPBAR32(PORTARB + 0x00) = 0x01000001;
 269         EPBAR32(PORTARB + 0x04) = 0x00040000;
 270         EPBAR32(PORTARB + 0x08) = 0x00001000;
 271         EPBAR32(PORTARB + 0x0c) = 0x00000040;
 272         EPBAR32(PORTARB + 0x10) = 0x01000001;
 273         EPBAR32(PORTARB + 0x14) = 0x00040000;
 274         EPBAR32(PORTARB + 0x18) = 0x00001000;
 275         EPBAR32(PORTARB + 0x1c) = 0x00000040;
 276
 277         EPBAR32(EPVC1RCTL) |= (1 << 16);
 278         EPBAR32(EPVC1RCTL) |= (1 << 16);
 279
 280         printk(BIOS_DEBUG, "Loading port arbitration table ...");
 281         /* Loop until bit 0 becomes 0 */
 282         timeout = 0x7fffff;
 283         while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) ;
 284         if (!timeout)
 285                 printk(BIOS_DEBUG, "timeout!\n");
 286         else
 287                 printk(BIOS_DEBUG, "ok\n");
 288
 289         /* Now enable VC1 */
 290         EPBAR32(EPVC1RCTL) |= (1 << 31);
 291
 292         printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
 293         /* Wait for VC1 negotiation pending */
 294         timeout = 0x7fff;
 295         while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) ;
 296         if (!timeout)
 297                 printk(BIOS_DEBUG, "timeout!\n");
 298         else
 299                 printk(BIOS_DEBUG, "ok\n");
 300
 301 }
 302
 303 static void ich7_setup_dmi_rcrb(void)
 304 {
 305         u16 reg16;
 306         u32 reg32;
 307
 308         reg16 = RCBA16(LCTL);
 309         reg16 &= ~(3 << 0);
 310         reg16 |= 3;
 311         RCBA16(LCTL) = reg16;
 312
 313         RCBA32(V0CTL) = 0x80000001;
 314         RCBA32(V1CAP) = 0x03128010;
 315         RCBA32(ESD) = 0x00000810;
 316         RCBA32(RP1D) = 0x01000003;
 317         RCBA32(RP2D) = 0x02000002;
 318         RCBA32(RP3D) = 0x03000002;
 319         RCBA32(RP4D) = 0x04000002;
 320         RCBA32(HDD) = 0x0f000003;
 321         RCBA32(RP5D) = 0x05000002;
 322
 323         RCBA32(RPFN) = 0x00543210;
 324
 325         pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141);
 326         pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141);
 327         pci_write_config16(PCI_DEV(0, 0x1c, 5), 0x42, 0x0141);
 328
 329         pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0);
 330         pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0);
 331
 332         reg32 = RCBA32(V1CTL);
 333         reg32 &= ~( (0x7f << 1) | (7 << 17) | (7 << 24) );
 334         reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31);
 335         RCBA32(V1CTL) = reg32;
 336
 337         RCBA32(ESD) |= (2 << 16);
 338
 339         RCBA32(ULD) |= (1 << 24) | (1 << 16);
 340
 341         RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR;
 342
 343         RCBA32(RP1D) |= (2 << 16);
 344         RCBA32(RP2D) |= (2 << 16);
 345         RCBA32(RP3D) |= (2 << 16);
 346         RCBA32(RP4D) |= (2 << 16);
 347         RCBA32(HDD)  |= (2 << 16);
 348         RCBA32(RP5D) |= (2 << 16);
 349         RCBA32(RP6D) |= (2 << 16);
 350
 351         RCBA32(LCAP) |= (3 << 10);
 352 }
 353
 354 static void i945_setup_dmi_rcrb(void)
 355 {
 356         u32 reg32;
 357         u32 timeout;
 358         int activate_aspm = 1; /* hardcode ASPM for now */
 359
 360         printk(BIOS_DEBUG, "Setting up DMI RCRB\n");
 361
 362         /* Virtual Channel 0 Configuration */
 363         reg32 = DMIBAR32(DMIVC0RCTL0);
 364         reg32 &= 0xffffff01;
 365         DMIBAR32(DMIVC0RCTL0) = reg32;
 366
 367         reg32 = DMIBAR32(DMIPVCCAP1);
 368         reg32 &= ~(7 << 0);
 369         reg32 |= 1;
 370         DMIBAR32(DMIPVCCAP1) = reg32;
 371
 372         reg32 = DMIBAR32(DMIVC1RCTL);
 373         reg32 &= ~(7 << 24);
 374         reg32 |= (1 << 24);     /* NOTE: This ID must match ICH7 side */
 375         DMIBAR32(DMIVC1RCTL) = reg32;
 376
 377         reg32 = DMIBAR32(DMIVC1RCTL);
 378         reg32 &= 0xffffff01;
 379         reg32 |= (1 << 7);
 380         DMIBAR32(DMIVC1RCTL) = reg32;
 381
 382         /* Now enable VC1 */
 383         DMIBAR32(DMIVC1RCTL) |= (1 << 31);
 384
 385         printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
 386         /* Wait for VC1 negotiation pending */
 387         timeout = 0x7ffff;
 388         while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) ;
 389         if (!timeout)
 390                 printk(BIOS_DEBUG, "timeout!\n");
 391         else
 392                 printk(BIOS_DEBUG, "done..\n");
 393 #if 1
 394         /* Enable Active State Power Management (ASPM) L0 state */
 395
 396         reg32 = DMIBAR32(DMILCAP);
 397         reg32 &= ~(7 << 12);
 398         reg32 |= (2 << 12);
 399
 400         reg32 &= ~(7 << 15);
 401
 402         reg32 |= (2 << 15);
 403         DMIBAR32(DMILCAP) = reg32;
 404
 405         reg32 = DMIBAR32(DMICC);
 406         reg32 &= 0x00ffffff;
 407         reg32 &= ~(3 << 0);
 408         reg32 |= (1 << 0);
 409         reg32 &= ~(3 << 20);
 410         reg32 |= (1 << 20);
 411
 412         DMIBAR32(DMICC) = reg32;
 413
 414         if (activate_aspm) {
 415                 DMIBAR32(DMILCTL) |= (3 << 0);
 416         }
 417 #endif
 418
 419         /* Last but not least, some additional steps */
 420         reg32 = MCHBAR32(FSBSNPCTL);
 421         reg32 &= ~(0xff << 2);
 422         reg32 |= (0xaa << 2);
 423         MCHBAR32(FSBSNPCTL) = reg32;
 424
 425         DMIBAR32(0x2c) = 0x86000040;
 426
 427         reg32 = DMIBAR32(0x204);
 428         reg32 &= ~0x3ff;
 429 #if 1
 430         reg32 |= 0x13f;         /* for x4 DMI only */
 431 #else
 432         reg32 |= 0x1e4; /* for x2 DMI only */
 433 #endif
 434         DMIBAR32(0x204) = reg32;
 435
 436         if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
 437                 printk(BIOS_DEBUG, "Internal graphics: enabled\n");
 438                 DMIBAR32(0x200) |= (1 << 21);
 439         } else {
 440                 printk(BIOS_DEBUG, "Internal graphics: disabled\n");
 441                 DMIBAR32(0x200) &= ~(1 << 21);
 442         }
 443
 444         reg32 = DMIBAR32(0x204);
 445         reg32 &= ~((1 << 11) | (1 << 10));
 446         DMIBAR32(0x204) = reg32;
 447
 448         reg32 = DMIBAR32(0x204);
 449         reg32 &= ~(0xff << 12);
 450         reg32 |= (0x0d << 12);
 451         DMIBAR32(0x204) = reg32;
 452
 453         DMIBAR32(DMICTL1) |= (3 << 24);
 454
 455         reg32 = DMIBAR32(0x200);
 456         reg32 &= ~(0x3 << 26);
 457         reg32 |= (0x02 << 26);
 458         DMIBAR32(0x200) = reg32;
 459
 460         DMIBAR32(DMIDRCCFG) &= ~(1 << 31);
 461         DMIBAR32(DMICTL2) |= (1 << 31);
 462
 463         if (i945_silicon_revision() >= 3) {
 464                 reg32 = DMIBAR32(0xec0);
 465                 reg32 &= 0x0fffffff;
 466                 reg32 |= (2 << 28);
 467                 DMIBAR32(0xec0) = reg32;
 468
 469                 reg32 = DMIBAR32(0xed4);
 470                 reg32 &= 0x0fffffff;
 471                 reg32 |= (2 << 28);
 472                 DMIBAR32(0xed4) = reg32;
 473
 474                 reg32 = DMIBAR32(0xee8);
 475                 reg32 &= 0x0fffffff;
 476                 reg32 |= (2 << 28);
 477                 DMIBAR32(0xee8) = reg32;
 478
 479                 reg32 = DMIBAR32(0xefc);
 480                 reg32 &= 0x0fffffff;
 481                 reg32 |= (2 << 28);
 482                 DMIBAR32(0xefc) = reg32;
 483         }
 484
 485         /* wait for bit toggle to 0 */
 486         printk(BIOS_DEBUG, "Waiting for DMI hardware...");
 487         timeout = 0x7fffff;
 488         while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) ;
 489         if (!timeout)
 490                 printk(BIOS_DEBUG, "timeout!\n");
 491         else
 492                 printk(BIOS_DEBUG, "ok\n");
 493
 494         /* Clear Error Status Bits! */
 495         DMIBAR32(0x1c4) = 0xffffffff;
 496         DMIBAR32(0x1d0) = 0xffffffff;
 497         DMIBAR32(0x228) = 0xffffffff;
 498
 499         /* Program Read-Only Write-Once Registers */
 500         DMIBAR32(0x308) = DMIBAR32(0x308);
 501         DMIBAR32(0x314) = DMIBAR32(0x314);
 502         DMIBAR32(0x324) = DMIBAR32(0x324);
 503         DMIBAR32(0x328) = DMIBAR32(0x328);
 504         DMIBAR32(0x338) = DMIBAR32(0x334);
 505         DMIBAR32(0x338) = DMIBAR32(0x338);
 506
 507         if (i945_silicon_revision() == 1 && (MCHBAR8(DFT_STRAP1) & (1 << 5))) {
 508                 if ((MCHBAR32(0x214) & 0xf) != 0x3) {
 509                         printk(BIOS_INFO, "DMI link requires A1 stepping workaround. Rebooting.\n");
 510                         reg32 = DMIBAR32(0x224);
 511                         reg32 &= ~(7 << 0);
 512                         reg32 |= (3 << 0);
 513                         DMIBAR32(0x224) = reg32;
 514                         outb(0x06, 0xcf9);
 515                         halt(); /* wait for reset */
 516                 }
 517         }
 518 }
 519
 520 static void i945_setup_pci_express_x16(void)
 521 {
 522         u32 timeout;
 523         u32 reg32;
 524         u16 reg16;
 525
 526         u8 reg8;
 527
 528         printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n");
 529
 530         reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
 531         reg16 |= DEVEN_D1F0;
 532         pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16);
 533
 534         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x208);
 535         reg32 &= ~(1 << 8);
 536         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32);
 537
 538         /* We have no success with querying the usual PCIe registers
 539          * for link setup success on the i945. Hence we assign a temporary
 540          * PCI bus 0x0a and check whether we find a device on 0:a.0
 541          */
 542
 543         /* First we reset the secondary bus */
 544         reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
 545         reg16 |= (1 << 6); /* SRESET */
 546         pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
 547         /* Read back and clear reset bit. */
 548         reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
 549         reg16 &= ~(1 << 6); /* SRESET */
 550         pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
 551
 552         reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);
 553         printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
 554         if (!(reg16 & 0x48)) {
 555                 goto disable_pciexpress_x16_link;
 556         }
 557         reg16 |= (1 << 4) | (1 << 0);
 558         pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16);
 559
 560         pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x00);
 561         pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x00);
 562         pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x0a);
 563         pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x0a);
 564
 565         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224);
 566         reg32 &= ~(1 << 8);
 567         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
 568
 569         MCHBAR16(UPMC1) &= ~( (1 << 5) | (1 << 0) );
 570
 571         /* Initialze PEG_CAP */
 572         reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xa2);
 573         reg16 |= (1 << 8);
 574         pci_write_config16(PCI_DEV(0, 0x01, 0), 0xa2, reg16);
 575
 576         /* Setup SLOTCAP */
 577         /* TODO: These values are mainboard dependent and should
 578          * be set from devicetree.cb.
 579          */
 580         /* NOTE: SLOTCAP becomes RO after the first write! */
 581         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xb4);
 582         reg32 &= 0x0007ffff;
 583
 584         reg32 &= 0xfffe007f;
 585
 586         pci_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32);
 587
 588         /* Wait for training to succeed */
 589         printk(BIOS_DEBUG, "PCIe link training ...");
 590         timeout = 0x7ffff;
 591         while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3)  && --timeout) ;
 592
 593         reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
 594         if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
 595                 printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n",
 596                                 reg32 & 0xffff, reg32 >> 16);
 597         } else {
 598                 printk(BIOS_DEBUG, " timeout!\n");
 599
 600                 printk(BIOS_DEBUG, "Restrain PCIe port to x1\n");
 601
 602                 reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS);
 603                 reg32 &= ~(0xf << 1);
 604                 reg32 |=1;
 605                 pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32);
 606
 607                 reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
 608
 609                 reg16 |= (1 << 6);
 610                 pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
 611                 reg16 &= ~(1 << 6);
 612                 pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
 613
 614                 printk(BIOS_DEBUG, "PCIe link training ...");
 615                 timeout = 0x7ffff;
 616                 while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3)  && --timeout) ;
 617
 618                 reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
 619                 if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
 620                         printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n",
 621                                 reg32 & 0xffff, reg32 >> 16);
 622                 } else {
 623                         printk(BIOS_DEBUG, " timeout!\n");
 624                         printk(BIOS_DEBUG, "Disabling PCIe x16 port completely.\n");
 625                         goto disable_pciexpress_x16_link;
 626                 }
 627         }
 628
 629         reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xb2);
 630         reg16 >>= 4;
 631         reg16 &= 0x3f;
 632         /* reg16 == 1 -> x1; reg16 == 16 -> x16 */
 633         printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16);
 634
 635         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x204);
 636         reg32 &= 0xfffffc00; /* clear [9:0] */
 637         if (reg16 == 1) {
 638                 reg32 |= 0x32b;
 639                 // TODO
 640                 /* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */
 641         } else if (reg16 == 16) {
 642                 reg32 |= 0x0f4;
 643                 // TODO
 644                 /* pci_write_config32(PCI_DEV(0, 0x01, 0), 0x204, reg32); */
 645         }
 646
 647         reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8);
 648         printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32);
 649         if (reg32 == 0x030000) {
 650                 printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n");
 651                 reg16 = (1 << 1);
 652                 pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16);
 653
 654                 reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN);
 655                 reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1);
 656                 pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32);
 657
 658                 /* Set VGA enable bit in PCIe bridge */
 659                 reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), 0x3e);
 660                 reg16 |= (1 << 3);
 661                 pci_write_config16(PCI_DEV(0, 0x1, 0), 0x3e, reg16);
 662         }
 663
 664         /* Enable GPEs */
 665         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xec);
 666         reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */
 667         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32);
 668
 669         /* Virtual Channel Configuration: Only VC0 on PCIe x16 */
 670         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x114);
 671         reg32 &= 0xffffff01;
 672         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32);
 673
 674         /* Extended VC count */
 675         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x104);
 676         reg32 &= ~(7 << 0);
 677         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x104, reg32);
 678
 679         /* Active State Power Management ASPM */
 680
 681         /* TODO */
 682
 683         /* Clear error bits */
 684         pci_write_config16(PCI_DEV(0, 0x01, 0), 0x06, 0xffff);
 685         pci_write_config16(PCI_DEV(0, 0x01, 0), 0x1e, 0xffff);
 686         pci_write_config16(PCI_DEV(0, 0x01, 0), 0xaa, 0xffff);
 687         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1c4, 0xffffffff);
 688         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1d0, 0xffffffff);
 689         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff);
 690         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff);
 691
 692         /* Program R/WO registers */
 693         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x308);
 694         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x308, reg32);
 695
 696         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x314);
 697         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x314, reg32);
 698
 699         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x324);
 700         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x324, reg32);
 701
 702         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328);
 703         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32);
 704
 705         reg8 = pci_read_config8(PCI_DEV(0, 0x01, 0), 0xb4);
 706         pci_write_config8(PCI_DEV(0, 0x01, 0), 0xb4, reg8);
 707
 708         /* Additional PCIe graphics setup */
 709         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0);
 710         reg32 |= (3 << 26);
 711         pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32);
 712
 713         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0);
 714         reg32 |= (3 << 24);
 715         pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32);
 716
 717         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0);
 718         reg32 |= (1 << 5);
 719         pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32);
 720
 721         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x200);
 722         reg32 &= ~(3 << 26);
 723         reg32 |= (2 << 26);
 724         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32);
 725
 726         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80);
 727         if (i945_silicon_revision() >= 2) {
 728                 reg32 |= (1 << 12);
 729         } else {
 730                 reg32 &= ~(1 << 12);
 731         }
 732         pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32);
 733
 734         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4);
 735         reg32 &= ~(1 << 31);
 736         pci_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32);
 737
 738         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xfc);
 739         reg32 |= (1 << 31);
 740         pci_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32);
 741
 742         if (i945_silicon_revision() >= 3) {
 743                 static const u32 reglist[] = {
 744                         0xec0, 0xed4, 0xee8, 0xefc, 0xf10, 0xf24,
 745                         0xf38, 0xf4c, 0xf60, 0xf74, 0xf88, 0xf9c,
 746                         0xfb0, 0xfc4, 0xfd8, 0xfec
 747                 };
 748
 749                 int i;
 750                 for (i=0; i<ARRAY_SIZE(reglist); i++) {
 751                         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]);
 752                         reg32 &= 0x0fffffff;
 753                         reg32 |= (2 << 28);
 754                         pci_write_config32(PCI_DEV(0, 0x01, 0), reglist[i], reg32);
 755                 }
 756         }
 757
 758         if (i945_silicon_revision() <= 2 ) {
 759                 /* Set voltage specific parameters */
 760                 reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80);
 761                 reg32 &= (0xf << 4);    /* Default case 1.05V */
 762                 if ((MCHBAR32(DFT_STRAP1) & (1 << 20)) == 0) {  /* 1.50V */
 763                         reg32 |= (7 << 4);
 764                 }
 765                 pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32);
 766         }
 767
 768         return;
 769
 770 disable_pciexpress_x16_link:
 771         /* For now we just disable the x16 link */
 772         printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n");
 773
 774         MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
 775
 776         reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
 777         reg16 |= (1 << 6);
 778         pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
 779
 780         reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224);
 781         reg32 |= (1 << 8);
 782         pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
 783
 784         reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1);
 785         reg16 &= ~(1 << 6);
 786         pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
 787
 788         printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
 789         timeout = 0x7fffff;
 790         for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS);
 791              (reg32 & 0x000f0000) && --timeout;) ;
 792         if (!timeout)
 793                 printk(BIOS_DEBUG, "timeout!\n");
 794         else
 795                 printk(BIOS_DEBUG, "ok\n");
 796
 797         /* Finally: Disable the PCI config header */
 798         reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
 799         reg16 &= ~DEVEN_D1F0;
 800         pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16);
 801 }
 802
 803 static void i945_setup_root_complex_topology(void)
 804 {
 805         u32 reg32;
 806
 807         printk(BIOS_DEBUG, "Setting up Root Complex Topology\n");
 808         /* Egress Port Root Topology */
 809
 810         reg32 = EPBAR32(EPESD);
 811         reg32 &= 0xff00ffff;
 812         reg32 |= (1 << 16);
 813         EPBAR32(EPESD) = reg32;
 814
 815         EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0);
 816
 817         EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR;
 818
 819         EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0);
 820
 821         /* DMI Port Root Topology */
 822
 823         reg32 = DMIBAR32(DMILE1D);
 824         reg32 &= 0x00ffffff;
 825
 826         reg32 &= 0xff00ffff;
 827         reg32 |= (2 << 16);
 828
 829         reg32 |= (1 << 0);
 830         DMIBAR32(DMILE1D) = reg32;
 831
 832         DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA;
 833
 834         DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0);
 835
 836         DMIBAR32(DMILE2A) = DEFAULT_EPBAR;
 837
 838         /* PCI Express x16 Port Root Topology */
 839         if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) {
 840                 pci_write_config32(PCI_DEV(0, 0x01, 0), 0x158, DEFAULT_EPBAR);
 841                 reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x150);
 842                 reg32 |= (1 << 0);
 843                 pci_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32);
 844         }
 845 }
 846
 847 static void ich7_setup_root_complex_topology(void)
 848 {
 849         RCBA32(0x104) = 0x00000802;
 850         RCBA32(0x110) = 0x00000001;
 851         RCBA32(0x114) = 0x00000000;
 852         RCBA32(0x118) = 0x00000000;
 853 }
 854
 855 static void ich7_setup_pci_express(void)
 856 {
 857         RCBA32(CG) |= (1 << 0);
 858
 859         /* Initialize slot power limit for root ports */
 860         pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060);
 861 #if 0
 862         pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0);
 863         pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0);
 864 #endif
 865
 866         pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000);
 867 }
 868
 869 void i945_early_initialization(void)
 870 {
 871         /* Print some chipset specific information */
 872         switch (pci_read_config32(PCI_DEV(0, 0x00, 0), 0)) {
 873         case 0x27708086: /* 82945G/GZ/GC/P/PL */
 874                 i945_detect_chipset();
 875                 break;
 876         case 0x27a08086: /* 945GME/GSE */
 877         case 0x27ac8086: /* 945GM/PM/GMS/GU/GT, 943/940GML */
 878                 i945m_detect_chipset();
 879                 break;
 880         }
 881
 882         /* Setup all BARs required for early PCIe and raminit */
 883         i945_setup_bars();
 884
 885         /* Change port80 to LPC */
 886         RCBA32(GCS) &= (~0x04);
 887
 888         /* Just do it that way */
 889         RCBA32(0x2010) |= (1 << 10);
 890 }
 891
 892 static void i945_prepare_resume(int s3resume)
 893 {
 894         int cbmem_was_initted;
 895
 896         cbmem_was_initted = !cbmem_recovery(s3resume);
 897
 898         /* If there is no high memory area, we didn't boot before, so
 899          * this is not a resume. In that case we just create the cbmem toc.
 900          */
 901         if (s3resume && cbmem_was_initted) {
 902                 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 903
 904                 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
 905                  * through stage 2. We could keep stuff like stack and heap in high tables
 906                  * memory completely, but that's a wonderful clean up task for another
 907                  * day.
 908                  */
 909                 if (resume_backup_memory)
 910                         memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE,
 911                                HIGH_MEMORY_SAVE);
 912
 913                 /* Magic for S3 resume */
 914                 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD,
 915                                    SKPAD_ACPI_S3_MAGIC);
 916         }
 917 }
 918
 919 void i945_late_initialization(int s3resume)
 920 {
 921         i945_setup_egress_port();
 922
 923         ich7_setup_root_complex_topology();
 924
 925         ich7_setup_pci_express();
 926
 927         ich7_setup_dmi_rcrb();
 928
 929         i945_setup_dmi_rcrb();
 930
 931         i945_setup_pci_express_x16();
 932
 933         i945_setup_root_complex_topology();
 934
 935 #if !CONFIG_HAVE_ACPI_RESUME
 936 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 937 #if CONFIG_DEBUG_RAM_SETUP
 938         sdram_dump_mchbar_registers();
 939
 940         {
 941                 /* This will not work if TSEG is in place! */
 942                 u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM);
 943
 944                 printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 945                 ram_check(0x00000000, 0x000a0000);
 946                 ram_check(0x00100000, tom);
 947         }
 948 #endif
 949 #endif
 950 #endif
 951
 952         MCHBAR16(SSKPD) = 0xCAFE;
 953
 954         i945_prepare_resume(s3resume);
 955 }