src/northbridge/intel/haswell/haswell.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2008 coresystems GmbH
   5  * Copyright (C) 2011 Google Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__
  18 #define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__
  19
  20 /* Chipset types */
  21 #define HASWELL_MOBILE  0
  22 #define HASWELL_DESKTOP 1
  23 #define HASWELL_SERVER  2
  24
  25 /* Intel Enhanced Debug region */
  26 #define IED_SIZE        CONFIG_IED_REGION_SIZE
  27
  28 /* Northbridge BARs */
  29 #define DEFAULT_PCIEXBAR        CONFIG_MMCONF_BASE_ADDRESS      /* 4 KB per PCIe device */
  30 #define DEFAULT_MCHBAR          0xfed10000      /* 16 KB */
  31 #ifndef __ACPI__
  32 #define DEFAULT_DMIBAR          ((u8 *)0xfed18000)      /* 4 KB */
  33 #else
  34 #define DEFAULT_DMIBAR          0xfed18000      /* 4 KB */
  35 #endif
  36 #define DEFAULT_EPBAR           0xfed19000      /* 4 KB */
  37
  38 #include <southbridge/intel/lynxpoint/pch.h>
  39
  40 /* Everything below this line is ignored in the DSDT */
  41 #ifndef __ACPI__
  42
  43 /* Device 0:0.0 PCI configuration space (Host Bridge) */
  44
  45 #define EPBAR           0x40
  46 #define MCHBAR          0x48
  47 #define PCIEXBAR        0x60
  48 #define DMIBAR          0x68
  49
  50 #define GGC             0x50                    /* GMCH Graphics Control */
  51
  52 #define DEVEN           0x54                    /* Device Enable */
  53 #define  DEVEN_D7EN     (1 << 14)
  54 #define  DEVEN_D4EN     (1 << 7)
  55 #define  DEVEN_D3EN     (1 << 5)
  56 #define  DEVEN_D2EN     (1 << 4)
  57 #define  DEVEN_D1F0EN   (1 << 3)
  58 #define  DEVEN_D1F1EN   (1 << 2)
  59 #define  DEVEN_D1F2EN   (1 << 1)
  60 #define  DEVEN_D0EN     (1 << 0)
  61
  62 #define PAM0            0x80
  63 #define PAM1            0x81
  64 #define PAM2            0x82
  65 #define PAM3            0x83
  66 #define PAM4            0x84
  67 #define PAM5            0x85
  68 #define PAM6            0x86
  69
  70 #define LAC             0x87    /* Legacy Access Control */
  71 #define SMRAM           0x88    /* System Management RAM Control */
  72 #define  D_OPEN         (1 << 6)
  73 #define  D_CLS          (1 << 5)
  74 #define  D_LCK          (1 << 4)
  75 #define  G_SMRAME       (1 << 3)
  76 #define  C_BASE_SEG     ((0 << 2) | (1 << 1) | (0 << 0))
  77
  78 #define MESEG_BASE      0x70    /* Management Engine Base. */
  79 #define MESEG_LIMIT     0x78    /* Management Engine Limit. */
  80 #define REMAPBASE       0x90    /* Remap base. */
  81 #define REMAPLIMIT      0x98    /* Remap limit. */
  82 #define TOM             0xa0    /* Top of DRAM in memory controller space. */
  83 #define TOUUD           0xa8    /* Top of Upper Usable DRAM */
  84 #define BDSM            0xb0    /* Base Data Stolen Memory */
  85 #define BGSM            0xb4    /* Base GTT Stolen Memory */
  86 #define TSEG            0xb8    /* TSEG base */
  87 #define TOLUD           0xbc    /* Top of Low Used Memory */
  88
  89 #define SKPAD           0xdc    /* Scratchpad Data */
  90
  91 /* Device 0:1.0 PCI configuration space (PCI Express) */
  92
  93 #define BCTRL1          0x3e    /* 16bit */
  94
  95
  96 /* Device 0:2.0 PCI configuration space (Graphics Device) */
  97
  98 #define MSAC            0x62    /* Multi Size Aperture Control */
  99 #define SWSCI           0xe8    /* SWSCI  enable */
 100 #define ASLS            0xfc    /* OpRegion Base */
 101
 102 /*
 103  * MCHBAR
 104  */
 105
 106 #define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
 107 #define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
 108 #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
 109 #define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or))
 110
 111 #define BIOS_RESET_CPL  0x5da8  /* 8bit */
 112
 113 /* Some power MSRs are also represented in MCHBAR */
 114 #define MCH_PKG_POWER_LIMIT_LO  0x59a0
 115 #define MCH_PKG_POWER_LIMIT_HI  0x59a4
 116 #define MCH_DDR_POWER_LIMIT_LO  0x58e0
 117 #define MCH_DDR_POWER_LIMIT_HI  0x58e4
 118
 119 /*
 120  * EPBAR - Egress Port Root Complex Register Block
 121  */
 122
 123 #define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
 124 #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
 125 #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
 126
 127 #define EPPVCCAP1       0x004   /* 32bit */
 128 #define EPPVCCAP2       0x008   /* 32bit */
 129
 130 #define EPVC0RCAP       0x010   /* 32bit */
 131 #define EPVC0RCTL       0x014   /* 32bit */
 132 #define EPVC0RSTS       0x01a   /* 16bit */
 133
 134 #define EPVC1RCAP       0x01c   /* 32bit */
 135 #define EPVC1RCTL       0x020   /* 32bit */
 136 #define EPVC1RSTS       0x026   /* 16bit */
 137
 138 #define EPVC1MTS        0x028   /* 32bit */
 139 #define EPVC1IST        0x038   /* 64bit */
 140
 141 #define EPESD           0x044   /* 32bit */
 142
 143 #define EPLE1D          0x050   /* 32bit */
 144 #define EPLE1A          0x058   /* 64bit */
 145 #define EPLE2D          0x060   /* 32bit */
 146 #define EPLE2A          0x068   /* 64bit */
 147
 148 #define PORTARB         0x100   /* 256bit */
 149
 150 /*
 151  * DMIBAR
 152  */
 153
 154 #define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
 155 #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
 156 #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
 157
 158 #define DMIVCECH        0x000   /* 32bit */
 159 #define DMIPVCCAP1      0x004   /* 32bit */
 160 #define DMIPVCCAP2      0x008   /* 32bit */
 161
 162 #define DMIPVCCCTL      0x00c   /* 16bit */
 163
 164 #define DMIVC0RCAP      0x010   /* 32bit */
 165 #define DMIVC0RCTL0     0x014   /* 32bit */
 166 #define DMIVC0RSTS      0x01a   /* 16bit */
 167
 168 #define DMIVC1RCAP      0x01c   /* 32bit */
 169 #define DMIVC1RCTL      0x020   /* 32bit */
 170 #define DMIVC1RSTS      0x026   /* 16bit */
 171
 172 #define DMILE1D         0x050   /* 32bit */
 173 #define DMILE1A         0x058   /* 64bit */
 174 #define DMILE2D         0x060   /* 32bit */
 175 #define DMILE2A         0x068   /* 64bit */
 176
 177 #define DMILCAP         0x084   /* 32bit */
 178 #define DMILCTL         0x088   /* 16bit */
 179 #define DMILSTS         0x08a   /* 16bit */
 180
 181 #define DMICTL1         0x0f0   /* 32bit */
 182 #define DMICTL2         0x0fc   /* 32bit */
 183
 184 #define DMICC           0x208   /* 32bit */
 185
 186 #define DMIDRCCFG       0xeb4   /* 32bit */
 187
 188 #ifndef __ASSEMBLER__
 189 static inline void barrier(void) { asm("" ::: "memory"); }
 190
 191 struct ied_header {
 192         char signature[10];
 193         u32 size;
 194         u8 reserved[34];
 195 } __attribute__ ((packed));
 196
 197 #define PCI_DEVICE_ID_HSW_MOBILE 0x0c04
 198 #define PCI_DEVICE_ID_HSW_ULT 0x0a04
 199
 200 #ifdef __SMM__
 201 void intel_northbridge_haswell_finalize_smm(void);
 202 #else /* !__SMM__ */
 203 void haswell_early_initialization(int chipset_type);
 204 void haswell_late_initialization(void);
 205 void set_translation_table(int start, int end, u64 base, int inc);
 206
 207 /* debugging functions */
 208 void print_pci_devices(void);
 209 void dump_pci_device(unsigned dev);
 210 void dump_pci_devices(void);
 211 void dump_spd_registers(void);
 212 void dump_mem(unsigned start, unsigned end);
 213 void report_platform_info(void);
 214 #endif /* !__SMM__ */
 215
 216
 217 #define MRC_DATA_ALIGN           0x1000
 218 #define MRC_DATA_SIGNATURE       (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
 219
 220 struct mrc_data_container {
 221         u32     mrc_signature;  // "MRCD"
 222         u32     mrc_data_size;  // Actual total size of this structure
 223         u32     mrc_checksum;   // IP style checksum
 224         u32     reserved;       // For header alignment
 225         u8      mrc_data[0];    // Variable size, platform/run time dependent.
 226 } __attribute__ ((packed));
 227
 228 struct mrc_data_container *find_current_mrc_cache(void);
 229 #if !defined(__PRE_RAM__)
 230 #include "gma.h"
 231 int init_igd_opregion(igd_opregion_t *igd_opregion);
 232 #endif
 233
 234 #endif
 235 #endif
 236 #endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */