src/northbridge/intel/fsp_sandybridge/northbridge_pci_devs.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013 Google Inc.
   5  * Copyright (C) 2014 Sage Electronic Engineering, LLC.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef _INTEL_FSP_SANDYBRIDGE_PCI_DEVS_H_
  18 #define _INTEL_FSP_SANDYBRIDGE_PCI_DEVS_H_
  19
  20 #include <device/pci_def.h>
  21
  22 #define BUS0 0
  23
  24 /* NB PCIe PEG slot */
  25 #define NB_PEG_DEV              0x01
  26 #define NB_PEG_FUNC             0
  27 # define NB_PEG_DEVFN   PCI_DEVFN(NB_PEG_DEV, NB_PEG_FUNC)
  28 #define PCIE_CTRL1_FUNC 1
  29 # define PCIE_CTRL1_DEVFN       PCI_DEVFN(NB_PEG_DEV, PCIE_CTRL1_FUNC)
  30 #define PCIE_CTRL2_FUNC 2
  31 # define PCIE_CTRL2_DEVFN       PCI_DEVFN(NB_PEG_DEV, PCIE_CTRL2_FUNC)
  32
  33 /* Onboard Graphics */
  34 #define GFX_DEV         0x02
  35 #define GFX_FUNC        0
  36 # define GFX_DEVFN      PCI_DEVFN(GFX_DEV, GFX_FUNC)
  37
  38 /* NB PCIe slot */
  39 #define NB_PCIE_DEV             0x06
  40 #define NB_PCIE_FUNC    0
  41 # define NB_PCIE_DEVFN  PCI_DEVFN(NB_PCIE_DEV, NB_PCIE_FUNC)
  42
  43 #endif /* _INTEL_FSP_SANDYBRIDGE_PCI_DEVS_H_ */