2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
6 * Copyright (C) 2013 Sage Electronic Engineering, LLC.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <console/console.h>
19 #include <arch/acpi.h>
23 #include <cpu/intel/fsp_model_206ax/model_206ax.h>
24 #include <cpu/x86/msr.h>
25 #include <device/device.h>
26 #include <device/pci.h>
27 #include <device/pci_ids.h>
28 #include <device/hypertransport.h>
34 #include "northbridge.h"
36 #include <cpu/intel/smm/gen1/smi.h>
38 static int bridge_revision_id
= -1;
41 static uint64_t uma_memory_base
= 0;
42 static uint64_t uma_memory_size
= 0;
44 int bridge_silicon_revision(void)
46 if (bridge_revision_id
< 0) {
47 uint8_t stepping
= cpuid_eax(1) & 0xf;
48 uint8_t bridge_id
= pci_read_config16(
49 dev_find_slot(0, PCI_DEVFN(0, 0)),
50 PCI_DEVICE_ID
) & 0xf0;
51 bridge_revision_id
= bridge_id
| stepping
;
53 return bridge_revision_id
;
56 /* Reserve everything between A segment and 1MB:
58 * 0xa0000 - 0xbffff: legacy VGA
59 * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
60 * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
62 static const int legacy_hole_base_k
= 0xa0000 / 1024;
63 static const int legacy_hole_size_k
= 384;
65 static int get_pcie_bar(u32
*base
, u32
*len
)
73 dev
= dev_find_slot(0, PCI_DEVFN(0, 0));
77 pciexbar_reg
= pci_read_config32(dev
, PCIEXBAR
);
79 if (!(pciexbar_reg
& (1 << 0)))
82 switch ((pciexbar_reg
>> 1) & 3) {
84 *base
= pciexbar_reg
& ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
85 *len
= 256 * 1024 * 1024;
88 *base
= pciexbar_reg
& ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
89 *len
= 128 * 1024 * 1024;
92 *base
= pciexbar_reg
& ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
93 *len
= 64 * 1024 * 1024;
100 static void add_fixed_resources(struct device
*dev
, int index
)
102 struct resource
*resource
;
103 u32 pcie_config_base
, pcie_config_size
;
105 mmio_resource(dev
, index
++, uma_memory_base
>> 10, uma_memory_size
>> 10);
107 if (get_pcie_bar(&pcie_config_base
, &pcie_config_size
)) {
108 printk(BIOS_DEBUG
, "Adding PCIe config bar base=0x%08x "
109 "size=0x%x\n", pcie_config_base
, pcie_config_size
);
110 resource
= new_resource(dev
, index
++);
111 resource
->base
= (resource_t
) pcie_config_base
;
112 resource
->size
= (resource_t
) pcie_config_size
;
113 resource
->flags
= IORESOURCE_MEM
| IORESOURCE_RESERVE
|
114 IORESOURCE_FIXED
| IORESOURCE_STORED
| IORESOURCE_ASSIGNED
;
117 mmio_resource(dev
, index
++, legacy_hole_base_k
, legacy_hole_size_k
);
120 static void pci_domain_set_resources(device_t dev
)
122 uint64_t tom
, me_base
, touud
;
123 uint32_t tseg_base
, uma_size
, tolud
;
125 unsigned long long tomk
;
127 tomk
= ggc
= tseg_base
= uma_size
= tolud
= tom
= me_base
= touud
= 0;
129 /* Total Memory 2GB example:
131 * 00000000 0000MB-1992MB 1992MB RAM (writeback)
132 * 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
133 * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
134 * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
135 * 7f200000 2034MB TOLUD
136 * 7f800000 2040MB MEBASE
137 * 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
138 * 80000000 2048MB TOM
139 * 100000000 4096MB-4102MB 6MB RAM (writeback)
141 * Total Memory 4GB example:
143 * 00000000 0000MB-2768MB 2768MB RAM (writeback)
144 * ad000000 2768MB-2776MB 8MB TSEG (SMRR)
145 * ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
146 * ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
147 * afa00000 2810MB TOLUD
148 * ff800000 4088MB MEBASE
149 * ff800000 4088MB-4096MB 8MB ME UMA (uncached)
150 * 100000000 4096MB TOM
151 * 100000000 4096MB-5374MB 1278MB RAM (writeback)
152 * 14fe00000 5368MB TOUUD
155 /* Top of Upper Usable DRAM, including remap */
156 touud
= pci_read_config32(dev
, TOUUD
+4);
158 touud
|= pci_read_config32(dev
, TOUUD
) & ~(1UL << 0);
160 /* Top of Lower Usable DRAM */
161 tolud
= pci_read_config32(dev
, TOLUD
) & ~(1UL << 0);
163 /* Top of Memory - does not account for any UMA */
164 tom
= pci_read_config32(dev
, 0xa4);
166 tom
|= pci_read_config32(dev
, 0xa0) & ~(1UL << 0);
168 printk(BIOS_DEBUG
, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
171 /* ME UMA needs excluding if total memory <4GB */
172 me_base
= pci_read_config32(dev
, 0x74);
174 me_base
|= pci_read_config32(dev
, 0x70);
176 printk(BIOS_DEBUG
, "MEBASE 0x%llx\n", me_base
);
179 if (me_base
== tolud
) {
180 /* ME is from MEBASE-TOM */
181 uma_size
= (tom
- me_base
) >> 10;
182 /* Increment TOLUD to account for ME as RAM */
183 tolud
+= uma_size
<< 10;
184 /* UMA starts at old TOLUD */
185 uma_memory_base
= tomk
* 1024ULL;
186 uma_memory_size
= uma_size
* 1024ULL;
187 printk(BIOS_DEBUG
, "ME UMA base 0x%llx size %uM\n",
188 me_base
, uma_size
>> 10);
191 /* Graphics memory comes next */
192 ggc
= pci_read_config16(dev
, GGC
);
194 printk(BIOS_DEBUG
, "IGD decoded, subtracting ");
196 /* Graphics memory */
197 uma_size
= ((ggc
>> 3) & 0x1f) * 32 * 1024ULL;
198 printk(BIOS_DEBUG
, "%uM UMA", uma_size
>> 10);
200 uma_memory_base
= tomk
* 1024ULL;
201 uma_memory_size
+= uma_size
* 1024ULL;
203 /* GTT Graphics Stolen Memory Size (GGMS) */
204 uma_size
= ((ggc
>> 8) & 0x3) * 1024ULL;
206 uma_memory_base
= tomk
* 1024ULL;
207 uma_memory_size
+= uma_size
* 1024ULL;
208 printk(BIOS_DEBUG
, " and %uM GTT\n", uma_size
>> 10);
211 /* Calculate TSEG size from its base which must be below GTT */
212 uma_memory_base
= tomk
* 1024ULL;
213 tseg_base
= pci_read_config32(dev
, 0xb8) & ~(1UL << 0);
214 uma_size
= (uma_memory_base
- tseg_base
) >> 10;
216 uma_memory_base
= tomk
* 1024ULL;
217 uma_memory_size
+= uma_size
* 1024ULL;
218 printk(BIOS_DEBUG
, "TSEG base 0x%08x size %uM\n",
219 tseg_base
, uma_size
>> 10);
221 printk(BIOS_INFO
, "Available memory below 4GB: %lluM\n", tomk
>> 10);
223 /* Report the memory regions */
224 ram_resource(dev
, 3, 0, legacy_hole_base_k
);
225 ram_resource(dev
, 4, legacy_hole_base_k
+ legacy_hole_size_k
,
226 (tomk
- (legacy_hole_base_k
+ legacy_hole_size_k
)));
229 * If >= 4GB installed then memory from TOLUD to 4GB
230 * is remapped above TOM, TOUUD will account for both
232 touud
>>= 10; /* Convert to KB */
233 if (touud
> 4096 * 1024) {
234 ram_resource(dev
, 5, 4096 * 1024, touud
- (4096 * 1024));
235 printk(BIOS_INFO
, "Available memory above 4GB: %lluM\n",
236 (touud
>> 10) - 4096);
239 add_fixed_resources(dev
, 6);
241 assign_resources(dev
->link_list
);
244 /* TODO We could determine how many PCIe busses we need in
245 * the bar. For now that number is hardcoded to a max of 64.
246 * See e7525/northbridge.c for an example.
248 static struct device_operations pci_domain_ops
= {
249 .read_resources
= pci_domain_read_resources
,
250 .set_resources
= pci_domain_set_resources
,
251 .enable_resources
= NULL
,
253 .scan_bus
= pci_domain_scan_bus
,
254 .ops_pci_bus
= pci_bus_default_ops
,
257 static void mc_read_resources(device_t dev
)
259 struct resource
*resource
;
261 pci_dev_read_resources(dev
);
263 /* So, this is one of the big mysteries in the coreboot resource
264 * allocator. This resource should make sure that the address space
265 * of the PCIe memory mapped config space bar. But it does not.
268 /* We use 0xcf as an unused index for our PCIe bar so that we find it again */
269 resource
= new_resource(dev
, 0xcf);
270 resource
->base
= DEFAULT_PCIEXBAR
;
271 resource
->size
= 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */
273 IORESOURCE_MEM
| IORESOURCE_FIXED
| IORESOURCE_STORED
|
275 printk(BIOS_DEBUG
, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
276 (unsigned long)(resource
->base
), (unsigned long)(resource
->base
+ resource
->size
));
279 static void mc_set_resources(device_t dev
)
281 struct resource
*resource
;
283 /* Report the PCIe BAR */
284 resource
= find_resource(dev
, 0xcf);
286 report_resource_stored(dev
, resource
, "<mmconfig>");
289 /* And call the normal set_resources */
290 pci_dev_set_resources(dev
);
293 static void intel_set_subsystem(device_t dev
, unsigned vendor
, unsigned device
)
295 if (!vendor
|| !device
) {
296 pci_write_config32(dev
, PCI_SUBSYSTEM_VENDOR_ID
,
297 pci_read_config32(dev
, PCI_VENDOR_ID
));
299 pci_write_config32(dev
, PCI_SUBSYSTEM_VENDOR_ID
,
300 ((device
& 0xffff) << 16) | (vendor
& 0xffff));
304 static void northbridge_init(struct device
*dev
)
309 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
310 * that BIOS has initialized memory and power management
312 bios_reset_cpl
= MCHBAR8(BIOS_RESET_CPL
);
314 MCHBAR8(BIOS_RESET_CPL
) = bios_reset_cpl
;
315 printk(BIOS_DEBUG
, "Set BIOS_RESET_CPL\n");
318 static u32
northbridge_get_base_reg(device_t dev
, int reg
)
322 value
= pci_read_config32(dev
, reg
);
323 /* Base registers are at 1MiB granularity. */
324 value
&= ~((1 << 20) - 1);
329 northbridge_get_tseg_base_and_size(u32
*tsegmb
, u32
*tseg_size
)
333 dev
= dev_find_slot(0, PCI_DEVFN(0, 0));
335 *tsegmb
= northbridge_get_base_reg(dev
, TSEG
);
336 bgsm
= northbridge_get_base_reg(dev
, BGSM
);
337 *tseg_size
= bgsm
- *tsegmb
;
340 void northbridge_write_smram(u8 smram
)
342 pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM
, smram
);
345 static struct pci_operations intel_pci_ops
= {
346 .set_subsystem
= intel_set_subsystem
,
349 static struct device_operations mc_ops
= {
350 .read_resources
= mc_read_resources
,
351 .set_resources
= mc_set_resources
,
352 .enable_resources
= pci_dev_enable_resources
,
353 .init
= northbridge_init
,
355 .ops_pci
= &intel_pci_ops
,
356 .acpi_fill_ssdt_generator
= generate_cpu_entries
,
359 static const struct pci_driver mc_driver_0100 __pci_driver
= {
361 .vendor
= PCI_VENDOR_ID_INTEL
,
365 static const struct pci_driver mc_driver __pci_driver
= {
367 .vendor
= PCI_VENDOR_ID_INTEL
,
368 .device
= 0x0104, /* Sandy bridge */
371 static const struct pci_driver mc_driver_1 __pci_driver
= {
373 .vendor
= PCI_VENDOR_ID_INTEL
,
374 .device
= 0x0154, /* Ivy bridge */
377 static void cpu_bus_init(device_t dev
)
379 initialize_cpus(dev
->link_list
);
382 static struct device_operations cpu_bus_ops
= {
383 .read_resources
= DEVICE_NOOP
,
384 .set_resources
= DEVICE_NOOP
,
385 .enable_resources
= DEVICE_NOOP
,
386 .init
= cpu_bus_init
,
390 static void enable_dev(device_t dev
)
392 /* Set the operations if it is a special bus type */
393 if (dev
->path
.type
== DEVICE_PATH_DOMAIN
) {
394 dev
->ops
= &pci_domain_ops
;
395 } else if (dev
->path
.type
== DEVICE_PATH_CPU_CLUSTER
) {
396 dev
->ops
= &cpu_bus_ops
;
400 struct chip_operations northbridge_intel_fsp_sandybridge_ops
= {
401 CHIP_NAME("Intel i7 (SandyBridge/IvyBridge) integrated Northbridge")
402 .enable_dev
= enable_dev
,