src/northbridge/intel/fsp_sandybridge/gma.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Chromium OS Authors
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <arch/io.h>
  17 #include <console/console.h>
  18 #include <delay.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <device/pci_ids.h>
  22
  23 #include "chip.h"
  24 #include "northbridge.h"
  25
  26
  27 /* some vga option roms are used for several chipsets but they only have one
  28  * PCI ID in their header. If we encounter such an option rom, we need to do
  29  * the mapping ourselfes
  30  */
  31
  32 u32 map_oprom_vendev(u32 vendev)
  33 {
  34         u32 new_vendev=vendev;
  35
  36         switch (vendev) {
  37         case 0x80860102:                /* GT1 Desktop */
  38         case 0x8086010a:                /* GT1 Server */
  39         case 0x80860112:                /* GT2 Desktop */
  40         case 0x80860116:                /* GT2 Mobile */
  41         case 0x80860122:                /* GT2 Desktop >=1.3GHz */
  42         case 0x80860126:                /* GT2 Mobile >=1.3GHz */
  43         case 0x80860166:                /* IVB */
  44                 new_vendev=0x80860106;  /* GT1 Mobile */
  45                 break;
  46         }
  47
  48         return new_vendev;
  49 }
  50
  51 static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
  52 {
  53         if (!vendor || !device) {
  54                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
  55                                 pci_read_config32(dev, PCI_VENDOR_ID));
  56         } else {
  57                 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
  58                                 ((device & 0xffff) << 16) | (vendor & 0xffff));
  59         }
  60 }
  61
  62 const struct i915_gpu_controller_info *
  63 intel_gma_get_controller_info(void)
  64 {
  65         device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
  66         if (!dev) {
  67                 return NULL;
  68         }
  69         struct northbridge_intel_fsp_sandybridge_config *chip = dev->chip_info;
  70         return &chip->gfx;
  71 }
  72
  73 static void gma_ssdt(device_t device)
  74 {
  75         const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
  76         if (!gfx) {
  77                 return;
  78         }
  79
  80         drivers_intel_gma_displays_ssdt_generate(gfx);
  81 }
  82
  83 static struct pci_operations gma_pci_ops = {
  84         .set_subsystem    = gma_set_subsystem,
  85 };
  86
  87 static struct device_operations gma_func0_ops = {
  88         .read_resources         = pci_dev_read_resources,
  89         .set_resources          = pci_dev_set_resources,
  90         .enable_resources       = pci_dev_enable_resources,
  91         .acpi_fill_ssdt_generator = gma_ssdt,
  92         .init                   = pci_dev_init,
  93         .scan_bus               = 0,
  94         .enable                 = 0,
  95         .ops_pci                = &gma_pci_ops,
  96 };
  97
  98 static const unsigned short gma_ids[] = {
  99         0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x166,
 100         0,
 101 };
 102 static const struct pci_driver gma_gt1_desktop __pci_driver = {
 103         .ops    = &gma_func0_ops,
 104         .vendor = PCI_VENDOR_ID_INTEL,
 105         .devices= gma_ids,
 106 };