src/northbridge/intel/e7501/e7501.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2005 Digital Design Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 /*
  18  * e7501.h: PCI configuration space for the Intel E7501 memory controller
  19  */
  20
  21 /************  D0:F0 ************/
  22 // Register offsets
  23 #define MAYBE_SMRBASE   0x14    /* System Memory RCOMP Base Address Register, 32 bit? (if similar to 855PM) */
  24 #define MCHCFGNS                0x52    /* MCH (scrubber) configuration register, 16 bit */
  25 #define DRB_ROW_0               0x60    /* DRAM Row Boundary register, 8 bit */
  26 #define DRB_ROW_1               0x61
  27 #define DRB_ROW_2               0x62
  28 #define DRB_ROW_3               0x63
  29 #define DRB_ROW_4               0x64
  30 #define DRB_ROW_5               0x65
  31 #define DRB_ROW_6               0x66
  32 #define DRB_ROW_7               0x67
  33
  34 #define DRA                             0x70    /* DRAM Row Attributes registers, 4 x 8 bit */
  35 #define DRT                             0x78    /* DRAM Timing register, 32 bit */
  36 #define DRC                             0x7C    /* DRAM Controller Mode register, 32 bit */
  37 #define MAYBE_DRDCTL    0x80    /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */
  38 #define CKDIS                   0x8C    /* Clock disable register, 8 bit */
  39 #define TOLM                    0xC4    /* Top of Low Memory register, 16 bit */
  40 #define REMAPBASE               0xC6    /* Remap Base Address register, 16 bit */
  41 #define REMAPLIMIT              0xC8    /* Remap Limit Address register, 16 bit */
  42 #define SKPD                    0xDE    /* Scratchpad register, 16 bit */
  43 #define MAYBE_MCHTST    0xF4    /* MCH Test Register, 32 bit? (if similar to 855PM) */
  44
  45 // CAS# Latency bits in the DRAM Timing (DRT) register
  46 #define DRT_CAS_2_5             (0<<4)
  47 #define DRT_CAS_2_0             (1<<4)
  48 #define DRT_CAS_MASK    (3<<4)
  49
  50 // Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register
  51 #define RAM_COMMAND_NOP                 (1<<4)
  52 #define RAM_COMMAND_PRECHARGE   (2<<4)
  53 #define RAM_COMMAND_MRS                 (3<<4)
  54 #define RAM_COMMAND_EMRS                (4<<4)
  55 #define RAM_COMMAND_CBR                 (6<<4)
  56 #define RAM_COMMAND_NORMAL              (7<<4)
  57
  58
  59 // RCOMP Memory Map offsets
  60 // Conjecture based on apparent similarity between E7501 and 855PM
  61 // Intel doc. 252613-003 describes these for 855PM
  62
  63 #define MAYBE_SMRCTL            0x20    /* System Memory RCOMP Control Register? */
  64 #define MAYBE_DQCMDSTR          0x30    /* Strength control for DQ and CMD signal groups? */
  65 #define MAYBE_CKESTR            0x31    /* Strength control for CKE signal group? */
  66 #define MAYBE_CSBSTR            0x32    /* Strength control for CS# signal group? */
  67 #define MAYBE_CKSTR                     0x33    /* Strength control for CK signal group? */
  68 #define MAYBE_RCVENSTR          0x34    /* Strength control for RCVEnOut# signal group? */
  69
  70 /************  D0:F1 ************/
  71 // Register offsets
  72 #define FERR_GLOBAL                     0x40    /* First global error register, 32 bits */
  73 #define NERR_GLOBAL                     0x44    /* Next global error register, 32 bits */
  74 #define DRAM_FERR                       0x80    /* DRAM first error register, 8 bits */
  75 #define DRAM_NERR                       0x82    /* DRAM next error register, 8 bits */