src/northbridge/amd/amdk8/util.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Vincent Legoll <vincent.legoll@gmail.com>
   5  * Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 /*
  18  * K8 northbridge utilities (dump routing registers).
  19  * Designed to be called at any time.
  20  * It can be called before RAM is set up by including this file.
  21  * It can be called after RAM is set up by including amdk8.h and enabling the
  22  * compilation of this file in src/northbridge/amd/amdk8/Makefile.inc.
  23  */
  24 #ifndef __PRE_RAM__
  25 #include <console/console.h>
  26 #include <device/pci.h>
  27 #include <device/pci_ops.h>
  28 #endif
  29 #include "amdk8.h"
  30
  31 /* Function 1 */
  32 /* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at
  33  * 0x78, 0xb8, and 0xd8
  34  */
  35 #define DRAM_ROUTE_START        0x40
  36 #define DRAM_ROUTE_END          0x78
  37 #define MMIO_ROUTE_START        0x80
  38 #define MMIO_ROUTE_END          0xb8
  39 #define PCIIO_ROUTE_START       0xc0
  40 #define PCIIO_ROUTE_END         0xd8
  41 #define CONFIG_ROUTE_START      0xe0
  42 #define CONFIG_ROUTE_END        0xec
  43
  44 #define PCI_IO_BASE0            0xc0
  45 #define PCI_IO_BASE1            0xc8
  46 #define PCI_IO_BASE2            0xd0
  47 #define PCI_IO_BASE3            0xd8
  48 #define PCI_IO_BASE_VGA_EN      (1 << 4)
  49 #define PCI_IO_BASE_NO_ISA      (1 << 5)
  50
  51 #define BITS(r, shift, mask) (((r>>shift)&mask))
  52
  53 /**
  54  * Return "R" if the register has read-enable bit set.
  55  */
  56 static const char *re(u32 i)
  57 {
  58         return ((i & 1) ? "R" : "");
  59 }
  60
  61 /**
  62  * Return "W" if the register has write-enable bit set.
  63  */
  64 static const char *we(u32 i)
  65 {
  66         return ((i & 1) ? "W" : "");
  67 }
  68
  69 /**
  70  * Return a string containing the interleave settings.
  71  */
  72 static const char *ileave(u32 base)
  73 {
  74         switch ((base >> 8) & 7) {
  75         case 0:
  76                 return "No interleave";
  77         case 1:
  78                 return "2 nodes";
  79         case 3:
  80                 return "4 nodes";
  81         case 7:
  82                 return "8 nodes";
  83         default:
  84                 return "Reserved";
  85         }
  86 }
  87
  88 /**
  89  * Return the node number.
  90  * For one case (config registers) these are not the right bit fields.
  91  */
  92 static int r_node(u32 reg)
  93 {
  94         return BITS(reg, 0, 0x7);
  95 }
  96
  97 /**
  98  * Return the link number.
  99  * For one case (config registers) these are not the right bit fields.
 100  */
 101 static int r_link(u32 reg)
 102 {
 103         return BITS(reg, 4, 0x3);
 104 }
 105
 106 /**
 107  * Print the DRAM routing info for one base/limit pair.
 108  *
 109  * Show base, limit, dest node, dest link on that node, read and write
 110  * enable, and interleave information.
 111  *
 112  * @param level Printing level
 113  * @param which Register number
 114  * @param base Base register
 115  * @param lim Limit register
 116  */
 117 static void showdram(int level, u8 which, u32 base, u32 lim)
 118 {
 119         printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n",
 120                which, (((u64) base & 0xffff0000) << 8),
 121                (((u64) lim & 0xffff0000) << 8) + 0xffffff,
 122                r_node(lim), re(base), we(base), ileave(base), (lim >> 8) & 3);
 123 }
 124
 125 /**
 126  * Print the config routing info for a config register.
 127  *
 128  * Show base, limit, dest node, dest link on that node, read and write
 129  * enable, and device number compare enable
 130  *
 131  * @param level Printing level
 132  * @param which Register number
 133  * @param reg Config register
 134  */
 135 static void showconfig(int level, u8 which, u32 reg)
 136 {
 137         /* Don't use r_node() and r_link() here. */
 138         printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n",
 139                which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff),
 140                BITS(reg, 4, 0x7), BITS(reg, 8, 0x3),
 141                re(reg), we(reg),
 142                BITS(reg, 2, 0x1)?"dev":"bus");
 143 }
 144
 145 /**
 146  * Print the PCIIO routing info for one base/limit pair.
 147  *
 148  * Show base, limit, dest node, dest link on that node, read and write
 149  * enable, and VGA and ISA Enable.
 150  *
 151  * @param level Printing level
 152  * @param which Register number
 153  * @param base Base register
 154  * @param lim Limit register
 155  */
 156 static void showpciio(int level, u8 which, u32 base, u32 lim)
 157 {
 158         printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n",
 159                which, BITS(base, 12, 0x3fff) << 12,
 160                (BITS(lim, 12, 0x3fff) << 12) + 0xfff, r_node(lim), r_link(lim),
 161                re(base), we(base), BITS(base, 4, 0x1), BITS(base, 5, 0x1));
 162 }
 163
 164 /**
 165  * Print the MMIO routing info for one base/limit pair.
 166  *
 167  * Show base, limit, dest node, dest link on that node, read and write
 168  * enable, and CPU Disable, Lock, and Non-posted.
 169  *
 170  * @param level Printing level
 171  * @param which Register number
 172  * @param base Base register
 173  * @param lim Limit register
 174  */
 175 static void showmmio(int level, u8 which, u32 base, u32 lim)
 176 {
 177         printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, "
 178                "CPU disable %d, Lock %d, Non posted %d\n",
 179                which, ((u64) BITS(base, 0, 0xffffff00)) << 8,
 180                (((u64) BITS(lim, 0, 0xffffff00)) << 8) + 0xffff, r_node(lim),
 181                r_link(lim), re(base), we(base), BITS(base, 4, 0x1),
 182                BITS(base, 7, 0x1), BITS(lim, 7, 0x1));
 183 }
 184
 185 /**
 186  * Show all DRAM routing registers. This function is callable at any time.
 187  *
 188  * @param level The debug level.
 189  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
 190  *            raw config space.
 191  */
 192 static void showalldram(int level, device_t dev)
 193 {
 194         u8 reg;
 195         for (reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) {
 196                 u32 base = pci_read_config32(dev, reg);
 197                 u32 lim = pci_read_config32(dev, reg + 4);
 198                 if (base || lim!=(reg-DRAM_ROUTE_START)/8)
 199                         showdram(level, reg, base, lim);
 200         }
 201 }
 202
 203 /**
 204  * Show all MMIO routing registers. This function is callable at any time.
 205  *
 206  * @param level The debug level.
 207  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
 208  *            raw config space.
 209  */
 210 static void showallmmio(int level, device_t dev)
 211 {
 212         u8 reg;
 213         for (reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) {
 214                 u32 base = pci_read_config32(dev, reg);
 215                 u32 lim = pci_read_config32(dev, reg + 4);
 216                 if (base || lim)
 217                         showmmio(level, reg, base, lim);
 218         }
 219 }
 220
 221 /**
 222  * Show all PCIIO routing registers. This function is callable at any time.
 223  *
 224  * @param level The debug level.
 225  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
 226  *            raw config space.
 227  */
 228 static void showallpciio(int level, device_t dev)
 229 {
 230         u8 reg;
 231         for (reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) {
 232                 u32 base = pci_read_config32(dev, reg);
 233                 u32 lim = pci_read_config32(dev, reg + 4);
 234                 if (base || lim)
 235                         showpciio(level, reg, base, lim);
 236         }
 237 }
 238
 239 /**
 240  * Show all config routing registers. This function is callable at any time.
 241  *
 242  * @param level The debug level.
 243  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
 244  *            raw config space.
 245  */
 246 static void showallconfig(int level, device_t dev)
 247 {
 248         u8 reg;
 249         for (reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) {
 250                 u32 val = pci_read_config32(dev, reg);
 251                 if (val)
 252                         showconfig(level, reg, val);
 253         }
 254 }
 255
 256 /**
 257  * Show all routing registers. This function is callable at any time.
 258  *
 259  * @param level The debug level.
 260  * @param dev A 32-bit number in the standard bus/dev/fn format which is used
 261  *            raw config space.
 262  */
 263 void showallroutes(int level, device_t dev)
 264 {
 265         showalldram(level, dev);
 266         showallmmio(level, dev);
 267         showallpciio(level, dev);
 268         showallconfig(level, dev);
 269 }