src/northbridge/amd/amdht/h3ffeat.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16
  17 #ifndef H3FFEAT_H
  18 #define H3FFEAT_H
  19
  20 /*----------------------------------------------------------------------------
  21  *      Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
  22  *
  23  *----------------------------------------------------------------------------
  24  */
  25
  26 /*-----------------------------------------------------------------------------
  27  *                      DEFINITIONS AND MACROS
  28  *
  29  *-----------------------------------------------------------------------------
  30  */
  31
  32 #define MAX_NODES 8
  33 #define MAX_LINKS 8
  34 #define MAX_PLATFORM_LINKS 64 /* 8x8 fully connected (28) + 4 chains with two HT devices */
  35
  36 /* These following are internal definitions */
  37 #define ROUTETOSELF 0x0F
  38 #define INVALID_LINK 0xCC     /* Used in port list data structure to mark unused data entries.
  39                                   Can also be used for no link found in a port list search */
  40
  41 /* definitions for working with the port list structure */
  42 #define PORTLIST_TYPE_CPU 0
  43 #define PORTLIST_TYPE_IO  1
  44
  45 /*
  46  * Hypertransport Capability definitions and macros
  47  *
  48  */
  49
  50 /* HT Host Capability */
  51 /* bool isHTHostCapability(u32 reg) */
  52 #define IS_HT_HOST_CAPABILITY(reg) \
  53         ((reg & (u32)0xE00000FF) == (u32)0x20000008)
  54
  55 #define HT_HOST_CAP_SIZE                        0x20
  56
  57 /* Host CapabilityRegisters */
  58 #define HTHOST_LINK_CAPABILITY_REG              0x00
  59 #define HTHOST_LINK_CONTROL_REG         0x04
  60 #define HTHOST_FREQ_REV_REG                     0x08
  61         #define HT_HOST_REV_REV3                0x60
  62 #define HTHOST_FEATURE_CAP_REG                  0x0C
  63 #define HTHOST_BUFFER_COUNT_REG         0x10
  64 #define HTHOST_ISOC_REG                 0x14
  65 #define HTHOST_LINK_TYPE_REG                    0x18
  66         #define HTHOST_TYPE_COHERENT            3
  67         #define HTHOST_TYPE_NONCOHERENT 7
  68         #define HTHOST_TYPE_MASK                0x1F
  69
  70 /* HT Slave Capability (HT1 compat) */
  71 #define IS_HT_SLAVE_CAPABILITY(reg) \
  72         ((reg & (u32)0xE00000FF) == (u32)0x00000008)
  73 #define HTSLAVE_LINK01_OFFSET                   4
  74 #define HTSLAVE_LINK_CONTROL_0_REG              4
  75 #define HTSLAVE_FREQ_REV_0_REG                  0xC
  76
  77 /* HT3 gen Capability */
  78 #define IS_HT_GEN3_CAPABILITY(reg) \
  79         ((reg & (u32)0xF80000FF) == (u32)0xD0000008)
  80 #define HTGEN3_LINK01_OFFSET                    0x10
  81 #define HTGEN3_LINK_TRAINING_0_REG              0x10
  82
  83 /* HT3 Retry Capability */
  84 #define IS_HT_RETRY_CAPABILITY(reg) \
  85         ((reg & (u32)0xF80000FF) == (u32)0xC0000008)
  86
  87 #define HTRETRY_CONTROL_REG                     4
  88
  89 /* Unit ID Clumping Capability */
  90 #define IS_HT_UNITID_CAPABILITY(reg) \
  91         ((reg & (u32)0xF80000FF) == (u32)0x90000008)
  92
  93 #define HTUNIT_SUPPORT_REG                      4
  94 #define HTUNIT_ENABLE_REG                       8
  95
  96 /*----------------------------------------------------------------------------
  97  *                          TYPEDEFS, STRUCTURES, ENUMS
  98  *
  99  *----------------------------------------------------------------------------
 100  */
 101
 102 typedef struct cNorthBridge cNorthBridge;
 103
 104 /* A pair consists of a source node, a link to the destination node, the
 105  * destination node, and its link back to source node.   The even indices are
 106  * the source nodes and links, and the odd indices are for the destination
 107  * nodes and links.
 108  */
 109 typedef struct
 110 {
 111         /* This section is where the link is in the system and how to find it */
 112         u8 Type; /* 0 = CPU, 1 = Device, all others reserved */
 113         u8 Link; /* 0-1 for devices, 0-7 for CPUs */
 114         u8 NodeID; /* The node, or a pointer to the devices parent node */
 115         u8 HostLink, HostDepth; /* Link of parent node + depth in chain.  Only used by devices */
 116         SBDFO Pointer; /* A pointer to the device's slave HT capability, so we don't have to keep searching */
 117
 118         /* This section is for the final settings, which are written to hardware */
 119         BOOL SelRegang; /* Only used for CPU->CPU links */
 120         u8 SelWidthIn;
 121         u8 SelWidthOut;
 122         u8 SelFrequency;
 123
 124         /* This section is for keeping track of capabilities and possible configurations */
 125         BOOL RegangCap;
 126         u16 PrvFrequencyCap;
 127         u8 PrvWidthInCap;
 128         u8 PrvWidthOutCap;
 129         u16 CompositeFrequencyCap;
 130
 131 } sPortDescriptor;
 132
 133
 134 /*
 135  * Our global state data structure
 136  */
 137 typedef struct {
 138         AMD_HTBLOCK *HtBlock;
 139
 140         u8 NodesDiscovered;      /* One less than the number of nodes found in the system */
 141         u8 TotalLinks;
 142         u8 sysMpCap;             /* The maximum number of nodes that all processors are capable of */
 143
 144         /* Two ports for each link
 145          * Note: The Port pair 2*N and 2*N+1 are connected together to form a link
 146          * (e.g. 0,1 and 8,9 are ports on either end of an HT link) The lower number
 147          * port (2*N) is the source port.       The device that owns the source port is
 148          * always the device closer to the BSP. (i.e. nearer the CPU in a
 149          * non-coherent chain, or the CPU with the lower NodeID).
 150          */
 151         sPortDescriptor PortList[MAX_PLATFORM_LINKS*2];
 152
 153         /* The number of coherent links comming off of each node (i.e. the 'Degree' of the node) */
 154         u8 sysDegree[MAX_NODES];
 155         /* The systems adjency (sysMatrix[i][j] is true if Node_i has a link to Node_j) */
 156         BOOL sysMatrix[MAX_NODES][MAX_NODES];
 157
 158         /* Same as above, but for the currently selected database entry */
 159         u8 dbDegree[MAX_NODES];
 160         BOOL dbMatrix[MAX_NODES][MAX_NODES];
 161
 162         u8 Perm[MAX_NODES];      /* The node mapping from the database to the system */
 163         u8 ReversePerm[MAX_NODES];       /* The node mapping from the system to the database */
 164
 165         /* Data for non-coherent initilization */
 166         u8 AutoBusCurrent;
 167         u8 UsedCfgMapEntires;
 168
 169         /* 'This' pointer for northbridge */
 170         cNorthBridge *nb;
 171 } sMainData;
 172
 173 #endif   /* H3FFEAT_H */