tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / northbridge / amd / amdfam10 / setup_resource_map.c
blobcd2f71302eef9fa5d04fce44c5ca3bb1598ca9f9
1 /*
2 * This file is part of the coreboot project.
4 * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
5 * Copyright (C) 2007 Advanced Micro Devices, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #define RES_DEBUG 0
20 static void setup_resource_map(const u32 *register_values, u32 max)
22 u32 i;
23 // printk(BIOS_DEBUG, "setting up resource map....");
25 for(i = 0; i < max; i += 3) {
26 device_t dev;
27 u32 where;
28 u32 reg;
30 dev = register_values[i] & ~0xff;
31 where = register_values[i] & 0xff;
32 reg = pci_read_config32(dev, where);
33 reg &= register_values[i+1];
34 reg |= register_values[i+2];
35 pci_write_config32(dev, where, reg);
37 // printk(BIOS_DEBUG, "done.\n");
41 void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base)
43 u32 i;
44 // printk(BIOS_DEBUG, "setting up resource map offset....");
45 for(i = 0; i < max; i += 3) {
46 device_t dev;
47 u32 where;
48 unsigned long reg;
49 dev = (register_values[i] & ~0xfff) + offset_pci_dev;
50 where = register_values[i] & 0xfff;
51 reg = pci_read_config32(dev, where);
52 reg &= register_values[i+1];
53 reg |= register_values[i+2] + offset_io_base;
54 pci_write_config32(dev, where, reg);
56 // printk(BIOS_DEBUG, "done.\n");
59 #define RES_PCI_IO 0x10
60 #define RES_PORT_IO_8 0x22
61 #define RES_PORT_IO_32 0x20
62 #define RES_MEM_IO 0x40
64 void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base)
66 u32 i;
68 if (IS_ENABLED(RES_DEBUG))
69 printk(BIOS_DEBUG, "setting up resource map ex offset....\n");
71 for(i = 0; i < max; i += 4) {
72 if (IS_ENABLED(RES_DEBUG))
73 printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
74 i/4, register_values[i],
75 register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
76 register_values[i+2],
77 register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
79 switch (register_values[i]) {
80 case RES_PCI_IO: //PCI
82 device_t dev;
83 u32 where;
84 u32 reg;
85 dev = (register_values[i+1] & ~0xfff) + offset_pci_dev;
86 where = register_values[i+1] & 0xfff;
87 reg = pci_read_config32(dev, where);
88 if (IS_ENABLED(RES_DEBUG))
89 printk(BIOS_SPEW, "WAS: %08x\n", reg);
90 reg &= register_values[i+2];
91 reg |= register_values[i+3];
92 pci_write_config32(dev, where, reg);
93 if (IS_ENABLED(RES_DEBUG))
94 printk(BIOS_SPEW, "NOW: %08x\n", reg);
96 break;
97 case RES_PORT_IO_8: // io 8
99 u32 where;
100 u32 reg;
101 where = register_values[i+1] + offset_io_base;
102 reg = inb(where);
103 if (IS_ENABLED(RES_DEBUG))
104 printk(BIOS_SPEW, "WAS: %08x\n", reg);
105 reg &= register_values[i+2];
106 reg |= register_values[i+3];
107 outb(reg, where);
108 if (IS_ENABLED(RES_DEBUG))
109 printk(BIOS_SPEW, "NOW: %08x\n", reg);
111 break;
112 case RES_PORT_IO_32: //io32
114 u32 where;
115 u32 reg;
116 where = register_values[i+1] + offset_io_base;
117 reg = inl(where);
118 if (IS_ENABLED(RES_DEBUG))
119 printk(BIOS_SPEW, "WAS: %08x\n", reg);
120 reg &= register_values[i+2];
121 reg |= register_values[i+3];
122 outl(reg, where);
123 if (IS_ENABLED(RES_DEBUG))
124 printk(BIOS_SPEW, "NOW: %08x\n", reg);
126 break;
127 } // switch
132 if (IS_ENABLED(RES_DEBUG))
133 printk(BIOS_DEBUG, "done.\n");
136 void setup_resource_map_x(const u32 *register_values, u32 max)
138 u32 i;
140 if (IS_ENABLED(RES_DEBUG))
141 printk(BIOS_DEBUG, "setting up resource map ex offset....\n");
143 for(i = 0; i < max; i += 4) {
144 if (IS_ENABLED(RES_DEBUG))
145 printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
146 i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
147 switch (register_values[i]) {
148 case RES_PCI_IO: //PCI
150 device_t dev;
151 u32 where;
152 u32 reg;
153 dev = register_values[i+1] & ~0xff;
154 where = register_values[i+1] & 0xff;
155 reg = pci_read_config32(dev, where);
156 reg &= register_values[i+2];
157 reg |= register_values[i+3];
158 pci_write_config32(dev, where, reg);
160 break;
161 case RES_PORT_IO_8: // io 8
163 u32 where;
164 u32 reg;
165 where = register_values[i+1];
166 reg = inb(where);
167 reg &= register_values[i+2];
168 reg |= register_values[i+3];
169 outb(reg, where);
171 break;
172 case RES_PORT_IO_32: //io32
174 u32 where;
175 u32 reg;
176 where = register_values[i+1];
177 reg = inl(where);
178 reg &= register_values[i+2];
179 reg |= register_values[i+3];
180 outl(reg, where);
182 break;
183 } // switch
188 if (IS_ENABLED(RES_DEBUG))
189 printk(BIOS_DEBUG, "done.\n");
192 #if 0
193 static void setup_iob_resource_map(const u32 *register_values, u32 max)
195 u32 i;
197 for(i = 0; i < max; i += 3) {
198 u32 where;
199 u32 reg;
201 where = register_values[i];
202 reg = inb(where);
203 reg &= register_values[i+1];
204 reg |= register_values[i+2];
205 outb(reg, where);
209 static void setup_io_resource_map(const u32 *register_values, u32 max)
211 u32 i;
213 for(i = 0; i < max; i += 3) {
214 u32 where;
215 u32 reg;
217 where = register_values[i];
218 reg = inl(where);
219 reg &= register_values[i+1];
220 reg |= register_values[i+2];
222 outl(reg, where);
225 #endif