2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 static void setup_default_resource_map(void)
18 static const u32 register_values
[] = {
19 /* Careful set limit registers before base registers which contain
21 /* DRAM Limit i Registers
30 * [ 2: 0] Destination Node ID
40 * [10: 8] Interleave select
41 * specifies the values of A[14:12] to use with
44 * [31:16] DRAM Limit Address i Bits 39-24
45 * This field defines the upper address bits of a 40 bit
46 * address that define the end of the DRAM region.
48 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x44), 0x0000f8f8, 0x00000000,
49 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x4C), 0x0000f8f8, 0x00000001,
50 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x54), 0x0000f8f8, 0x00000002,
51 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x5C), 0x0000f8f8, 0x00000003,
52 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x64), 0x0000f8f8, 0x00000004,
53 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x6C), 0x0000f8f8, 0x00000005,
54 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x74), 0x0000f8f8, 0x00000006,
55 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x7C), 0x0000f8f8, 0x00000007,
56 /* DRAM Base i Registers
68 * [ 1: 1] Write Enable
72 * [10: 8] Interleave Enable
74 * 001 = Interleave on A[12] (2 nodes)
76 * 011 = Interleave on A[12] and A[14] (4 nodes)
80 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
82 * [13:16] DRAM Base Address i Bits 39-24
83 * This field defines the upper address bits of a 40-bit
84 * address that define the start of the DRAM region.
86 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x40), 0x0000f8fc, 0x00000000,
87 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x48), 0x0000f8fc, 0x00000000,
88 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x50), 0x0000f8fc, 0x00000000,
89 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x58), 0x0000f8fc, 0x00000000,
90 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x60), 0x0000f8fc, 0x00000000,
91 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x68), 0x0000f8fc, 0x00000000,
92 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x70), 0x0000f8fc, 0x00000000,
93 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x78), 0x0000f8fc, 0x00000000,
95 /* Memory-Mapped I/O Limit i Registers
104 * [ 2: 0] Destination Node ID
114 * [ 5: 4] Destination Link ID
121 * 0 = CPU writes may be posted
122 * 1 = CPU writes must be non-posted
123 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
124 * This field defines the upp adddress bits of a 40-bit
125 * address that defines the end of a memory-mapped
128 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x84), 0x00000048, 0x00000000,
129 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x8C), 0x00000048, 0x00000000,
130 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x94), 0x00000048, 0x00000000,
131 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x9C), 0x00000048, 0x00000000,
132 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xA4), 0x00000048, 0x00000000,
133 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xAC), 0x00000048, 0x00000000,
134 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xB4), 0x00000048, 0x00000000,
135 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xBC), 0x00000048, 0x00ffff00,
137 /* Memory-Mapped I/O Base i Registers
146 * [ 0: 0] Read Enable
149 * [ 1: 1] Write Enable
150 * 0 = Writes disabled
152 * [ 2: 2] Cpu Disable
153 * 0 = Cpu can use this I/O range
154 * 1 = Cpu requests do not use this I/O range
156 * 0 = base/limit registers i are read/write
157 * 1 = base/limit registers i are read-only
159 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
160 * This field defines the upper address bits of a 40bit
161 * address that defines the start of memory-mapped
164 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x80), 0x000000f0, 0x00000000,
165 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x88), 0x000000f0, 0x00000000,
166 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x90), 0x000000f0, 0x00000000,
167 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0x98), 0x000000f0, 0x00000000,
168 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xA0), 0x000000f0, 0x00000000,
169 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xA8), 0x000000f0, 0x00000000,
170 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xB0), 0x000000f0, 0x00000000,
171 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xB8), 0x000000f0, 0x00fc0003,
173 /* PCI I/O Limit i Registers
178 * [ 2: 0] Destination Node ID
188 * [ 5: 4] Destination Link ID
194 * [24:12] PCI I/O Limit Address i
195 * This field defines the end of PCI I/O region n
198 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xC4), 0xFE000FC8, 0x01fff000,
199 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xCC), 0xFE000FC8, 0x00000000,
200 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xD4), 0xFE000FC8, 0x00000000,
201 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xDC), 0xFE000FC8, 0x00000000,
203 /* PCI I/O Base i Registers
208 * [ 0: 0] Read Enable
211 * [ 1: 1] Write Enable
212 * 0 = Writes Disabled
216 * 0 = VGA matches Disabled
217 * 1 = matches all address < 64K and where A[9:0] is in
218 * the range 3B0-3BB or 3C0-3DF independent of the
219 * base & limit registers
221 * 0 = ISA matches Disabled
222 * 1 = Blocks address < 64K and in the last 768 bytes of
223 * eack 1K block from matching agains this base/limit
226 * [24:12] PCI I/O Base i
227 * This field defines the start of PCI I/O region n
230 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xC0), 0xFE000FCC, 0x00000003,
231 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xC8), 0xFE000FCC, 0x00000000,
232 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xD0), 0xFE000FCC, 0x00000000,
233 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xD8), 0xFE000FCC, 0x00000000,
235 /* Config Base and Limit i Registers
240 * [ 0: 0] Read Enable
243 * [ 1: 1] Write Enable
244 * 0 = Writes Disabled
246 * [ 2: 2] Device Number Compare Enable
247 * 0 = The ranges are based on bus number
248 * 1 = The ranges are ranges of devices on bus 0
250 * [ 6: 4] Destination Node
260 * [ 9: 8] Destination Link
266 * [23:16] Bus Number Base i
267 * This field defines the lowest bus number in
268 * configuration region i
269 * [31:24] Bus Number Limit i
270 * This field defines the highest bus number in
271 * configuration regin i
273 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xE0), 0x0000FC88, 0xff000003,
274 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xE4), 0x0000FC88, 0x00000000,
275 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xE8), 0x0000FC88, 0x00000000,
276 PCI_ADDR(CONFIG_CBB
, CONFIG_CDB
, 1, 0xEC), 0x0000FC88, 0x00000000,
280 max
= ARRAY_SIZE(register_values
);
281 setup_resource_map(register_values
, max
);