src/mainboard/via/vt8454c/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <stdint.h>
  18 #include <device/pci_def.h>
  19 #include <device/pci_ids.h>
  20 #include <arch/io.h>
  21 #include <device/pnp_def.h>
  22 #include <console/console.h>
  23 #include <lib.h>
  24 #include <northbridge/via/cx700/raminit.h>
  25 #include <cpu/x86/bist.h>
  26 #include "drivers/pc80/udelay_io.c"
  27 #include <delay.h>
  28 #include "northbridge/via/cx700/early_smbus.c"
  29 #include "lib/debug.c"
  30 #include "northbridge/via/cx700/early_serial.c"
  31 #include "northbridge/via/cx700/raminit.c"
  32 #include <spd.h>
  33
  34 static void enable_mainboard_devices(void)
  35 {
  36         device_t dev;
  37
  38         dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0);
  39         if (dev == PCI_DEV_INVALID) {
  40                 die("LPC bridge not found!!!\n");
  41         }
  42         // Disable GP3
  43         pci_write_config8(dev, 0x98, 0x00);
  44
  45         // Disable mc97
  46         pci_write_config8(dev, 0x50, 0x80);
  47
  48         // Disable internal KBC Configuration
  49         pci_write_config8(dev, 0x51, 0x2d);
  50         pci_write_config8(dev, 0x58, 0x42);
  51         pci_write_config8(dev, 0x59, 0x80);
  52         pci_write_config8(dev, 0x5b, 0x01);
  53
  54         // Enable P2P Bridge Header for External PCI BUS.
  55         dev = pci_locate_device(PCI_ID(0x1106, 0x324e), 0);
  56         if (dev == PCI_DEV_INVALID) {
  57                 die("P2P bridge not found!!!\n");
  58         }
  59         pci_write_config8(dev, 0x4f, 0x41);
  60
  61         // Switch SATA to non-RAID mode
  62         dev = pci_locate_device(PCI_ID(0x1106, 0x0581), 0);
  63         if (dev != PCI_DEV_INVALID) {
  64                 pci_write_config16(dev, 0xBA, 0x5324);
  65         }
  66 }
  67
  68 static void enable_shadow_ram(const struct mem_controller *ctrl)
  69 {
  70         u8 shadowreg;
  71
  72         pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a);
  73
  74         /* 0xf0000-0xfffff - ACPI tables */
  75         shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
  76         shadowreg |= 0x30;
  77         pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
  78 }
  79
  80 #include <cpu/intel/romstage.h>
  81 void main(unsigned long bist)
  82 {
  83         /* Set statically so it should work with cx700 as well */
  84         static const struct mem_controller cx700[] = {
  85                 {
  86                         .channel0 = {DIMM0, DIMM1},
  87                 },
  88         };
  89
  90         enable_smbus();
  91
  92         enable_cx700_serial();
  93         console_init();
  94
  95         /* Halt if there was a built in self test failure */
  96         report_bist_failure(bist);
  97
  98         enable_mainboard_devices();
  99
 100         /* Allows access to all northbridge devices */
 101         pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
 102
 103         sdram_set_registers(cx700);
 104         enable_shadow_ram(cx700);
 105         sdram_enable(cx700);
 106 }