2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 One Laptop per Child, Association, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 * Part of this file is from cx700 port, part of is from cn700 port,
18 * and acpi_is_wakeup_early_via_VX800() is part of Rudolf's S3 patch.
21 #define PAYLOAD_IS_SEABIOS 0
24 #include <device/pci_def.h>
25 #include <device/pci_ids.h>
26 #include <arch/acpi.h>
28 #include <device/pnp_def.h>
29 #include <console/console.h>
31 #include <northbridge/via/vx800/vx800.h>
32 #include <cpu/x86/bist.h>
33 #include "drivers/pc80/udelay_io.c"
36 /* This file contains the board-special SI value for raminit.c. */
37 #include "driving_clk_phase_data.c"
38 #include <northbridge/via/vx800/raminit.h>
39 #include "northbridge/via/vx800/raminit.c"
41 #include <superio/winbond/common/winbond.h>
42 #include <superio/winbond/w83697hf/w83697hf.h>
44 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
45 #define DUMMY_DEV PNP_DEV(0x2e, 0)
48 * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
49 * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html.
51 static int acpi_is_wakeup_early_via_vx800(void)
56 printk(BIOS_DEBUG
, "In acpi_is_wakeup_early_via_vx800\n");
57 /* Power management controller */
58 dev
= pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA
,
59 PCI_DEVICE_ID_VIA_VX855_LPC
), 0);
61 if (dev
== PCI_DEV_INVALID
)
62 die("Power management controller not found\n");
64 /* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */
65 pci_write_config16(dev
, 0x88, VX800_ACPI_IO_BASE
| 0x1);
67 /* Enable ACPI access RTC signal gated with PSON. */
68 pci_write_config8(dev
, 0x81, 0x84);
70 tmp
= inw(VX800_ACPI_IO_BASE
+ 0x04);
71 result
= ((tmp
& (7 << 10)) >> 10) == 1 ? 3 : 0;
72 printk(BIOS_DEBUG
, " boot_mode=%04x\n", result
);
76 /* All content of this function came from the cx700 port of coreboot. */
77 static void enable_mainboard_devices(void)
82 * Add and close this switch, since some line cause error, some
83 * written at elsewhere (stage1 stage2).
86 dev
= pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA
,
87 PCI_DEVICE_ID_VIA_VX855_LPC
), 0);
90 pci_write_config8(dev
, 0x98, 0x00);
92 pci_write_config8(dev
, 0x50, 0x80); /* Disable mc97. */
95 * Martin: Disable internal KBC configuration.
97 * Internal Config is needed to decide which key can be pressed to
100 pci_write_config8(dev
, 0x51, 0x2d);
102 /* This causes irq0 can not be triggerd, since bit 5 was set to 0. */
103 /* pci_write_config8(dev, 0x58, 0x42); */
105 /* These writing may... TODO */
106 regdata
= pci_read_config8(dev
, 0x58);
108 pci_write_config8(dev
, 0x58, regdata
);
109 pci_write_config8(dev
, 0x59, 0x80);
110 pci_write_config8(dev
, 0x5b, 0x01);
113 printk(BIOS_DEBUG
, "In enable_mainboard_devices\n");
115 /* Enable P2P Bridge Header for external PCI bus. */
116 dev
= pci_locate_device(PCI_ID(0x1106, 0xa353), 0);
117 pci_write_config8(dev
, 0x4f, 0x41);
120 * "5324" already is the default value of the PCI IDE device, cancel
123 * [william 20080124]: Fix bug that can not boot Ubuntu at the
128 dev
= pci_locate_device(PCI_ID(0x1106, PCI_DEVICE_ID_VIA_VX855_IDE
), 0);
131 values
= pci_read_config16(dev
, 0xBA);
134 pci_write_config16(dev
, 0xBA, values
);
139 * Most content of this function came from the cx700 port of coreboot.
140 * Turn on the shadow of E-seg.
142 static void enable_shadow_ram(void)
147 * Changed the value from 0x2a to 0x3f. "read only" may block "write"?
148 * and maybe in C-seg "write" will be needed?
150 pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff);
152 /* 0xf0000-0xfffff - ACPI tables */
153 shadowreg
= pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
155 pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg
);
157 /* 0xe0000-0xeffff - elfload? */
159 * In s3 resume process, wakeup.c, I use E-seg to hold the code
160 * (which can not locate in the area to be covered) that will copy
161 * 0-A-seg and F-seg from TOP-mem back to their normal location.
163 pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff);
166 /* Enable shadow RAM as normal DRAM */
167 /* 0xc0000-0xcffff - VGA BIOS */
168 pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0x2a);
169 pci_write_config8(PCI_DEV(0, 0, 7), 0x61, 0x00);
170 /* 0xd0000-0xdffff - ?? */
171 /* pci_write_config8(PCI_DEV(0, 0, 3), 0x81, 0xff); */
172 /* pci_write_config8(PCI_DEV(0, 0, 7), 0x62, 0xff); */
174 /* Do it again for the vlink controller. */
175 shadowreg
= pci_read_config8(PCI_DEV(0, 0, 7), 0x63);
177 pci_write_config8(PCI_DEV(0, 0, 7), 0x63, shadowreg
);
182 * Added this table 2008-11-28.
183 * This table contains the value needed to be set before begin to init DRAM.
184 * Note: REV_Bx should be checked for changes when porting a new board!
186 static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl
[] = {
187 /* VT3409 no PCI-E */
188 { 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E }, // Set Exxxxxxx as pcie mmio config range
189 { 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B }, // Support extended cfg address of pcie
190 // { 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02 }, // APIC Interrupt((BT_INTR)) Control
191 // Set ROMSIP value by software
194 { 0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33 }, // 2x Host Adr Strobe/Pad Pullup Driving = 3
195 { 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33 }, // 2x Host Adr Strobe/Pad Pulldown Driving = 3
196 { 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33 }, // 4x Host Dat Strobe/Pad Pullup Driving = 3
197 { 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33 }, // 4x Host Dat Strobe/Pad Pulldown Driving = 3
198 { 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21 }, // Memory I/F timing ctrl
199 { 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1 }, // Memory I/F timing ctrl
200 { 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18 }, // AGTL+ I/O Circuit
201 { 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C }, // AGTL+ Compensation Status
202 { 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33 }, // 2X AGTL+ Auto Compensation Offset
203 { 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33 }, // 4X AGTL+ Auto Compensation Offset
204 { 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72 }, // AGTL Compensation Status
205 { 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77 }, // AGTL Compensation Status
206 { 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44 }, // Input Host Address / Host Strobe Delay Control for HA Group
207 { 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22 }, // Input Host Address / Host Strobe Delay Control for HA Group
208 { 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00 }, // Output Delay Control of PAD for HA Group
209 { 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA }, // Host Address / Address Clock Output Delay Control (Only for P4 Bus)
210 { 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
211 { 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
212 { 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
213 { 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus)
214 { 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44 }, // Host Data Receiving Strobe Delay Ctrl 1
215 { 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44 }, // Host Data Receiving Strobe Delay Ctrl 2
216 { 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00 }, // Output Delay of PAD for HDSTB
217 { 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00 }, // Output Delay of PAD for HD
218 { 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 0)
219 { 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 1)
220 { 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 2)
221 { 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 3)
224 // CPU Host Bus Control
225 { 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08 }, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
226 // { 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F }, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
227 { 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C }, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW
228 { 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB }, // CPU I/F Ctrl-2: Enable all for performance
229 // { 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88 }, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK
230 { 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44 }, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK
231 { 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C }, // Misc Ctrl: Enable 8QW burst Mem Access
232 // { 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06 }, // Miscellaneous Control 2
233 { 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04 }, // Miscellaneous Control 2
234 { 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63 }, // Write Policy 1
235 // { 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01 }, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL
236 // { 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00 }, // CPU Miscellaneous Control 2
237 { 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2 }, // Write Policy
238 { 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88 }, // Bandwidth Timer
239 { 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46 }, // CPU Misc Ctrl
240 // { 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B }, // CPU Miscellaneous Control 3
241 // { 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B }, // CPU Miscellaneous Control 2
242 { 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A }, // CPU Miscellaneous Control 2
243 { 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41 }, // CPU Miscellaneous Control 3
244 { 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06 }, // CPU Miscellaneous Control 4
246 // Set APIC and SMRAM
247 { 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00 }, // APIC Related Control
248 { 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29 }, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg
249 { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } // End of the table
252 #define USE_VCP 1 /* 0 means "use DVP". */
256 #define gCom1Base 0x3f8
257 #define gCom2Base 0x2f8
260 static void EmbedComInit(void)
265 /* Enable NB multiple function control. */
266 ByteVal
= pci_read_config8(PCI_DEV(0, 0, 0), 0x4f);
267 ByteVal
= ByteVal
| 0x01;
268 pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, ByteVal
);
271 ByteVal
= pci_read_config8(PCI_DEV(0, 0, 3), 0xA1);
272 ByteVal
= ByteVal
| 0x80;
273 pci_write_config8(PCI_DEV(0, 0, 3), 0xA1, ByteVal
);
275 ByteVal
= pci_read_config8(PCI_DEV(0, 0, 3), 0xA7);
276 ByteVal
= ByteVal
| 0x08;
277 pci_write_config8(PCI_DEV(0, 0, 3), 0xA7, ByteVal
);
279 /* Enable P2P IO/mem. */
280 ByteVal
= pci_read_config8(PCI_DEV(0, 1, 0), 0x4);
281 ByteVal
= ByteVal
| 0x07;
282 pci_write_config8(PCI_DEV(0, 1, 0), 0x4, ByteVal
);
284 /* Turn on graphic chip I/O port port access. */
285 ByteVal
= inb(0x3C3);
286 ByteVal
= ByteVal
| 0x01;
287 outb(ByteVal
, 0x3C3);
289 /* Turn off graphic chip register protection. */
291 ByteVal
= inb(0x3C5);
292 ByteVal
= ByteVal
| 0x01;
293 outb(ByteVal
, 0x3C5);
295 /* South module pad share enable 0x3C5.78[7]. */
297 ByteVal
= inb(0x3C5);
298 ByteVal
= ByteVal
| 0x80;
299 outb(ByteVal
, 0x3C5);
301 /* Enable UART function multiplex with DVP or VCP pad D17F0Rx46[7,6]. */
302 ByteVal
= pci_read_config8(PCI_DEV(0, 17, 0), 0x46);
304 ByteVal
= (ByteVal
& 0x3F) | 0x40; /* Multiplex with VCP. */
306 ByteVal
= (ByteVal
& 0x3F) | 0xC0; /* Multiplex with DVP. */
307 pci_write_config8(PCI_DEV(0, 17, 0), 0x46, ByteVal
);
309 /* Enable embedded COM1 and COM2 D17F0RxB0[5,4]. */
310 ByteVal
= pci_read_config8(PCI_DEV(0, 17, 0), 0xB0);
311 ByteVal
= ByteVal
& 0xcf;
312 /* Multiplex with VCP. */
314 ByteVal
= ByteVal
| 0x10;
316 ByteVal
= ByteVal
| 0x20;
317 pci_write_config8(PCI_DEV(0, 17, 0), 0xB0, ByteVal
);
326 /* Set embedded COM1 I/O base = 0x3E8 (D17F0RB4, ByteVal = 0xFD) */
328 ByteVal
= (u8
) ((gCom1Base
>> 3) | 0x80);
329 pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal
);
330 ByteVal
= pci_read_config8(PCI_DEV(0, 17, 0), 0xb2);
331 ByteVal
= (ByteVal
& 0xf0) | 0x04;
332 pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal
);
335 /* Set embedded COM2 I/O base = 0x2E8 (D17F0RB5, ByteVal = 0xDD). */
337 ByteVal
= (u8
) ((gCom2Base
>> 3) | 0x80);
338 pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal
);
339 ByteVal
= pci_read_config8(PCI_DEV(0, 17, 0), 0xb2);
340 ByteVal
= (ByteVal
& 0x0f) | 0x30;
341 pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal
);
343 /* No port 80 biger then 0x10. */
345 /* Disable interrupt. */
346 ByteVal
= inb(ComBase
+ 3);
347 outb(ByteVal
& 0x7F, ComBase
+ 3);
348 outb(0x00, ComBase
+ 1);
351 ByteVal
= inb(ComBase
+ 3);
352 outb(ByteVal
| 0x80, ComBase
+ 3);
354 outb(0x00, ComBase
+ 1);
356 /* Set frame format. */
357 ByteVal
= inb(ComBase
+ 3);
358 outb(ByteVal
& 0x3F, ComBase
+ 3);
359 outb(0x03, ComBase
+ 3);
360 outb(0x00, ComBase
+ 2);
361 outb(0x00, ComBase
+ 4);
363 /* SOutput("Embedded COM output\n"); */
368 /* cache_as_ram.inc jumps to here. */
369 #include <cpu/intel/romstage.h>
370 void main(unsigned long bist
)
373 u8 rambits
, Data8
, Data
;
378 * Enable multifunction for northbridge. These 4 lines (until
379 * console_init()) are the same with epia-cn port.
381 pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
382 /* EmbedComInit(); */
383 w83697hf_set_clksel_48(DUMMY_DEV
);
384 winbond_enable_serial(SERIAL_DEV
, CONFIG_TTYS0_BASE
);
385 /* enable_vx800_serial(); */
404 pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBA,
405 PCI_DEVICE_ID_VIA_VX855_IDE
);
406 pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBE,
407 PCI_DEVICE_ID_VIA_VX855_IDE
);
408 pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA0, PCI_VENDOR_ID_VIA
);
409 pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA2,
410 PCI_DEVICE_ID_VIA_VX855_LPC
);
411 Data8
= pci_read_config8(PCI_DEV(0, 0x11, 0), 0x79);
414 pci_write_config8(PCI_DEV(0, 0x11, 0), 0x79, Data8
);
415 pci_write_config16(PCI_DEV(0, 0x11, 0), 0x72,
416 PCI_DEVICE_ID_VIA_VX855_LPC
);
419 * There are two function definitions of console_init(), while the
420 * src/arch/x86/lib is the right one.
424 /* Decide if this is a s3 wakeup or a normal boot. */
425 boot_mode
= acpi_is_wakeup_early_via_vx800();
428 * 2008-11-27 Add this, to transfer "cpu restart" to "cold boot".
429 * When this boot is not a S3 resume, and PCI registers had been
430 * written, then this must be a CPU restart (result of OS reboot cmd),
431 * so we need a real "cold boot".
434 && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) {
438 /* x86 cold boot I/O cmd. */
439 /* These 2 lines are the same with epia-cn port. */
442 /* This fix does help vx800!, but vx855 doesn't need this. */
443 /* smbus_fixup(&ctrl); */
445 /* Halt if there was a built-in self test failure. */
446 report_bist_failure(bist
);
448 printk(BIOS_DEBUG
, "Enabling mainboard devices\n");
449 enable_mainboard_devices();
452 * Get NB chip revision from D0F4RxF6, revision will be used in
455 device
= PCI_DEV(0, 0, 4);
456 Data
= pci_read_config8(device
, 0xf6);
457 printk(BIOS_DEBUG
, "NB chip revision = %02x\n", Data
);
459 /* Make NB ready before DRAM init. */
460 via_pci_inittable(Data
, mNbStage1InitTbl
);
463 * When resume from s3, DRAM init is skipped, so need to recovery
464 * any PCI register related to DRAM init. d0f3 didn't lose its power
465 * during whole s3 time, so any register not belonging to d0f3 needs
469 if (boot_mode
== 3) {
471 u8 ramregs
[] = { 0x43, 0x42, 0x41, 0x40 };
472 DRAM_SYS_ATTR DramAttr
;
474 printk(BIOS_DEBUG
, "This is an S3 wakeup\n");
476 memset(&DramAttr
, 0, sizeof(DRAM_SYS_ATTR
));
478 * Step 1: DRAM detection; DDR1 or DDR2; Get SPD Data;
479 * Rank Presence; 64 or 128bit; Unbuffered or registered;
482 DRAMDetect(&DramAttr
);
485 * Begin to get RAM size, 43,42 41 40 contains the end
486 * address of last rank in DDR2 slot.
488 device
= PCI_DEV(0, 0, 3);
489 for (rambits
= 0, i
= 0; i
< ARRAY_SIZE(ramregs
); i
++) {
490 rambits
= pci_read_config8(device
, ramregs
[i
]);
495 DRAMDRDYSetting(&DramAttr
);
497 Data
= 0x80; /* This value is same with DevInit.c. */
498 pci_write_config8(PCI_DEV(0, 0, 4), 0xa3, Data
);
499 pci_write_config8(PCI_DEV(0, 17, 7), 0x60, rambits
<< 2);
500 Data
= pci_read_config8(MEMCTRL
, 0x88);
501 pci_write_config8(PCI_DEV(0, 17, 7), 0xE5, Data
);
503 /* Just copy this function from draminit to here! */
504 DRAMRegFinalValue(&DramAttr
);
506 /* Just copy this function from draminit to here! */
509 printk(BIOS_DEBUG
, "Resume from S3, RAM init was ignored\n");
512 ram_check(0, 640 * 1024);
516 /* ddr2_ram_setup(); */
517 /* This line is the same with cx700 port. */
521 * For coreboot most time of S3 resume is the same as normal boot,
522 * so some memory area under 1M become dirty, so before this happen,
523 * I need to backup the content of mem to top-mem.
525 * I will reserve the 1M top-men in LBIO table in coreboot_table.c
526 * and recovery the content of 1M-mem in wakeup.c.
528 #if PAYLOAD_IS_SEABIOS == 1
529 if (boot_mode
== 3) {
530 /* An idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html
532 * I want move the 1M data, I have to set some MTRRs myself.
533 * Setting MTRR before back memory save s3 resume time about
536 * !!! Since CAR stack uses cache, and we are using cache
537 * here, we must be careful:
539 * 1. during this MTRR code, must no function call (after
540 * this MTRR, I think it should be OK to use function).
541 * 2. Before stack switch, no use variable that have value
543 * 3. Due to 2, take care of "cpu_reset", I directlly set it
546 u32 memtop
= *(u32
*) WAKE_MEM_INFO
;
547 u32 memtop1
= *(u32
*) WAKE_MEM_INFO
- 0x100000;
548 u32 memtop2
= *(u32
*) WAKE_MEM_INFO
- 0x200000;
549 u32 memtop3
= *(u32
*) WAKE_MEM_INFO
- 64 * 1024 - 0x100000;
551 *(u32
*) WAKE_MEM_INFO
- 64 * 1024 - 0x100000 + 0xe0000;
554 "movl $0x204, %%ecx\n\t"
555 "xorl %%edx, %%edx\n\t"
557 "orl $(0 | 6), %%eax\n\t"
560 "movl $0x205, %%ecx\n\t"
561 "xorl %%edx, %%edx\n\t"
562 "movl $0x100000,%%eax\n\t"
565 "orl $(0 | 0x800), %%eax\n\t"
571 "movl $0x206, %%ecx\n\t"
572 "xorl %%edx, %%edx\n\t"
574 "orl $(0 | 6), %%eax\n\t"
577 "movl $0x207, %%ecx\n\t"
578 "xorl %%edx, %%edx\n\t"
579 "movl $0x100000,%%eax\n\t"
582 "orl $(0 | 0x800), %%eax\n\t"
588 "movl $0x208, %ecx\n\t"
589 "xorl %edx, %edx\n\t"
591 "orl $(0 | 6), %eax\n\t"
594 "movl $0x209, %ecx\n\t"
595 "xorl %edx, %edx\n\t"
596 "movl $0x100000,%eax\n\t"
599 "orl $(0 | 0x800), %eax\n\t"
605 * WAKE_MEM_INFO is inited in get_set_top_available_mem()
606 * in tables.c these two memcpy() not not be enabled if set
607 * the MTRR around this two lines.
613 "movl $0xa0000, %%ecx\n\t"
620 "movl $0xe0000, %%esi\n\t"
622 "movl $0x20000, %%ecx\n\t"
628 /* This can have function call, because no variable used before this. */
629 printk(BIOS_DEBUG
, "Copy memory to high memory to protect s3 wakeup vector code\n");
630 memcpy((unsigned char *)((*(u32
*) WAKE_MEM_INFO
) - 64 * 1024 -
631 0x100000), (unsigned char *)0, 0xa0000);
632 memcpy((unsigned char *)((*(u32
*) WAKE_MEM_INFO
) - 64 * 1024 -
633 0x100000 + 0xe0000), (unsigned char *)0xe0000, 0x20000);
635 /* Restore the MTRR previously modified. */
639 "xorl %edx, %edx\n\t"
640 "xorl %eax, %eax\n\t"
641 "movl $0x204, %ecx\n\t"
643 "movl $0x205, %ecx\n\t"
645 "movl $0x206, %ecx\n\t"
647 "movl $0x207, %ecx\n\t"
649 "movl $0x208, %ecx\n\t"
651 "movl $0x209, %ecx\n\t"