src/mainboard/via/epia-m700/driving_clk_phase_data.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2009 One Laptop per Child, Association, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include "northbridge/via/vx800/driving_clk_phase_data.h"
  18
  19 // DQS Driving
  20 // Reg0xE0, 0xE1
  21 // According to #Bank to set DRAM DQS Driving
  22 // #Bank    1     2     3     4     5     6     7     8
  23 static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE };
  24 static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE };
  25
  26 // DQ Driving
  27 // Reg0xE2, 0xE3
  28 // For DDR2: According to bank to set DRAM DQ Driving
  29 static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC };
  30 static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA };
  31
  32 // CS Driving
  33 // Reg0xE4, 0xE5
  34 // According to #Bank to set DRAM CS Driving
  35 // DDR1 #Bank          1     2     3     4         5         6     7     8
  36 static const u8 DDR2_CSA_Driving_Table_x8[4] =  { 0x44, 0x44, 0x44, 0x44 };
  37 static const u8 DDR2_CSB_Driving_Table_x8[2] =  { 0x44, 0x44 };
  38 static const u8 DDR2_CSA_Driving_Table_x16[4] = { 0x44, 0x44, 0x44, 0x44 };
  39 static const u8 DDR2_CSB_Driving_Table_x16[2] = { 0x44, 0x44 };
  40
  41 // MAA Driving
  42 // Reg0xE8, Reg0xE9
  43 static const u8 DDR2_MAA_Driving_Table[MA_Table][5] = {
  44         // Chip number, 400,  533,  667   800    ;(SRAS, SCAS, SWE)RxE8
  45         {6,             0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06
  46         {18,            0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18
  47         {255,           0xDB, 0xDB, 0xDB, 0xDB}, // total MAA chips = 18 ~
  48 };
  49
  50 static const u8 DDR2_MAB_Driving_Table[MA_Table][2] = {
  51         // Chip number, Value                    ;(SRAS, SCAS, SWE)RxE9
  52         {6,             0x86},                   // total MAB chips = 00 ~ 06
  53         {18,            0x86},                   // total MAB chips = 06 ~ 18
  54         {255,           0xDB},                   // total MAB chips = 18 ~
  55 };
  56
  57 // DCLK Driving
  58 // Reg0xE6, 0xE7
  59 // For DDR2: According to #Freq to set DRAM DCLK Driving
  60 //                              freq            400M, 533M, 667M, 800M
  61 static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
  62 static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
  63
  64 /*
  65  * Duty cycle
  66  * Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB
  67  * D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF
  68  * According to DRAM frequency to control Duty Cycle
  69  */
  70 static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = {
  71         //    (And NOT) DDR800 DDR667 DDR533 DDR400
  72         //Reg  Mask  Value Value Value Value
  73         {0xEC, 0x00, 0x30, 0x30, 0x30, 0x30},   // 1Rank
  74         {0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00},
  75         {0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30},
  76 };
  77
  78 static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = {
  79         //    (And NOT) DDR800 DDR667 DDR533 DDR400
  80         //Reg  Mask  Value Value Value Value
  81         {0xED, 0x00, 0x88, 0x88, 0x84, 0x88},   // 1Rank
  82         {0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00},
  83         {0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00},
  84 };
  85
  86 /*
  87  * DRAM Clock Phase Control for FeedBack Mode
  88  * Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94
  89  * Processing:
  90  *   1. Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode.
  91  *   2. Program clock phase value with ChA/B DCLK enable,
  92  *      VIA_NB3DRAM_REG91[7:3]=00b
  93  *   3. Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO
  94  *      ChA DCLKO can't be disabled, so always program VIA_NB3DRAM_REG91[3]=0b.
  95  */
  96 static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = {
  97         //    (And NOT) DDR800 DDR667 DDR533 DDR400
  98         //Reg  Mask  Value Value Value Value
  99         {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07},   // 1Rank
 100         {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02},
 101         {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03},
 102 };
 103
 104 static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = {
 105         //    (And NOT) DDR800 DDR667 DDR533 DDR400
 106         //Reg  Mask  Value Value Value Value
 107         {0x91, 0x0F, 0x20, 0x10, 0x00, 0x70},   // 1Rank
 108         {0x92, 0x0F, 0x40, 0x30, 0x30, 0x20},
 109         {0x93, 0x0F, 0x60, 0x50, 0x40, 0x30},
 110 };
 111
 112 /* vt6413c */
 113 #if 0
 114 static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = {
 115         //     (And NOT) DDR800 DDR667 DDR533 DDR400
 116         //Reg  Mask  Value Value Value Value
 117         {0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 },  // 1Rank
 118         {0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 },
 119         {0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 },
 120 };
 121 #endif
 122
 123 /* vt6413d */
 124 static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = {
 125         //     (And NOT) DDR800 DDR667 DDR533 DDR400
 126         //Reg  Mask  Value Value Value Value
 127         {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07},   // 1Rank
 128         {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02},
 129         {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03},
 130 };
 131
 132 /*
 133  * DRAM Write Data phase control
 134  * Modify NB Reg: Rx74/Rx75/Rx76
 135  */
 136 /* vt6413c */
 137 #if 0
 138 static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = {
 139         //    (And NOT) DDR800 DDR667 DDR533 DDR400
 140         //Reg  Mask  Value Value Value Value
 141         {0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 },  // 1Rank
 142         {0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 },
 143         {0x76, 0x00, 0x10, 0x80, 0x00, 0x07 },
 144 };
 145 #endif
 146
 147 /* vt6413D */
 148 static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM][WrtData_FREQ_NUM] = {
 149         //    (And NOT) DDR800 DDR667 DDR533 DDR400
 150         //Reg  Mask  Value Value Value Value
 151         {0x74, 0xF8, 0x01, 0x00, 0x00, 0x07},   // 1Rank
 152         {0x75, 0xF8, 0x01, 0x00, 0x00, 0x07},
 153         {0x76, 0x10, 0x80, 0x87, 0x07, 0x06},
 154         {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03},
 155 };
 156
 157 #if 0
 158 static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = {
 159         //    (And NOT) DDR800 DDR667 DDR533 DDR400
 160         //Reg  Mask  Value Value Value Value
 161         {0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 },  // 1Rank
 162         {0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 },
 163         {0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 },
 164 };
 165 #endif
 166
 167 /*
 168  * DQ/DQS Output Delay Control
 169  * Modify NB D0F3: RxF0/RxF1/RxF2/RxF3
 170  */
 171 static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = {
 172         //RxF0 RxF1  RxF2  RxF3
 173         {0x00, 0x00, 0x00, 0x00},       /* DDR400 */
 174         {0x00, 0x00, 0x00, 0x00},       /* DDR533 */
 175         {0x00, 0x00, 0x00, 0x00},       /* DDR667 */
 176         {0x00, 0x00, 0x00, 0x00},       /* DDR800 */
 177 };
 178
 179 static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = {
 180         //RxF4 RxF5  RxF6  RxF7
 181         {0x00, 0x00, 0x00, 0x00},       /* DDR400 */
 182         {0x00, 0x00, 0x00, 0x00},       /* DDR533 */
 183         {0x00, 0x00, 0x00, 0x00},       /* DDR667 */
 184         {0x00, 0x00, 0x00, 0x00},       /* DDR800 */
 185 };
 186
 187 /*
 188  * DQ/DQS input Capture Control
 189  * modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B
 190  */
 191 /* vt6413C */
 192 #if 0
 193 static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = {
 194         //    (And NOT) DDR800 DDR667 DDR533 DDR400
 195         //Reg  Mask  Value Value Value Value
 196         {0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 },  // 1Rank
 197         {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 },
 198         {0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 }
 199 };
 200 #endif
 201
 202 /* vt6413D */
 203 static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = {
 204         //    (And NOT) DDR800 DDR667 DDR533 DDR400
 205         //Reg  Mask  Value Value Value Value
 206         {0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01},   // 1Rank
 207         {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00},
 208         {0x7B, 0x00, 0x34, 0x34, 0x20, 0x10}
 209 };
 210
 211 static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM][DQS_INPUT_CAPTURE_FREQ_NUM] = {
 212         //    (And NOT) DDR800 DDR667 DDR533 DDR400
 213         //Reg  Mask  Value Value Value Value
 214         {0x79, 0x00, 0x89, 0x89, 0x87, 0x83},   // 1Rank
 215         {0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00},
 216         {0x8B, 0x00, 0x34, 0x34, 0x20, 0x10}
 217 };
 218
 219 static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] = {
 220         //Rx70 Rx71
 221         {0x00, 0x05},           /* DDR800 */
 222         {0x00, 0x06},           /* DDR667 */
 223         {0x00, 0x04},           /* DDR533 */
 224         {0x00, 0x05},           /* DDR400 */
 225 };
 226
 227 static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] = {
 228         //Rx70 Rx71
 229         {0x00, 0x04},           /* DDR800 */
 230         {0x00, 0x04},           /* DDR667 */
 231         {0x00, 0x03},           /* DDR533 */
 232         {0x00, 0x04},           /* DDR400 */
 233 };