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tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / mainboard / tyan / s8226 / buildOpts.c
blob4a3d808e6e6d566cede714dbe33fe7b1f314a643
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <stdlib.h>
17
18 #include "AGESA.h"
19 #include "CommonReturns.h"
20 #include "AdvancedApi.h"
21 #include <PlatformMemoryConfiguration.h>
22 #include "Filecode.h"
23 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
24
25 /* AGESA will check the OEM configuration during preprocessing stage,
26 * coreboot enable -Wundef option, so we should make sure we have all contanstand defined
27 */
28 /* MEMORY_BUS_SPEED */
29 #define DDR400_FREQUENCY 200 ///< DDR 400
30 #define DDR533_FREQUENCY 266 ///< DDR 533
31 #define DDR667_FREQUENCY 333 ///< DDR 667
32 #define DDR800_FREQUENCY 400 ///< DDR 800
33 #define DDR1066_FREQUENCY 533 ///< DDR 1066
34 #define DDR1333_FREQUENCY 667 ///< DDR 1333
35 #define DDR1600_FREQUENCY 800 ///< DDR 1600
36 #define DDR1866_FREQUENCY 933 ///< DDR 1866
37 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
38
39 /* QUANDRANK_TYPE*/
40 #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
41 #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
42
43 /* USER_MEMORY_TIMING_MODE */
44 #define TIMING_MODE_AUTO 0 ///< Use best rate possible
45 #define TIMING_MODE_LIMITED 1 ///< Set user top limit
46 #define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
47
48 /* POWER_DOWN_MODE */
49 #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
50 #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
51
52 /* User makes option selections here
53 * Comment out the items wanted to be included in the build.
54 * Uncomment those items you with to REMOVE from the build.
55 */
56 //#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
57 //#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
58 //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
59 //#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
60 //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
61 //#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
62 //#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
63 //#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
64 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
65 //#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
66 ////#define BLDOPT_REMOVE_ACPI_PSTATES TRUE
67 ////#define BLDOPT_REMOVE_SRAT TRUE
68 ////#define BLDOPT_REMOVE_SLIT TRUE
69 //#define BLDOPT_REMOVE_WHEA TRUE
70 //#define BLDOPT_REMOVE_DMI TRUE
71
72 /*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */
73 #define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
74
75 //#define BLDOPT_REMOVE_HT_ASSIST TRUE
76 //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
77 //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
78 //#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
79 //#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
80 //#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
81 //#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
82
83 /* Build configuration values here.
84 */
85 #define BLDCFG_VRM_CURRENT_LIMIT 120000
86 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
87 #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0
88 #define BLDCFG_PLAT_NUM_IO_APICS 3
89 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
90 #define BLDCFG_MEM_INIT_PSTATE 0
91 #define BLDCFG_AMD_PSTATE_CAP_VALUE 0
92
93 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER
94
95 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY//1600
96 #define BLDCFG_MEMORY_MODE_UNGANGED TRUE
97 #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
98 #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
99 #define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
100 #define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
101 #define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
102 #define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE
103 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE//TRUE
104 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE//TRUE
105 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE//TRUE
106 #define BLDCFG_MEMORY_POWER_DOWN FALSE
107 #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL
108 #define BLDCFG_ONLINE_SPARE FALSE
109 #define BLDCFG_BANK_SWIZZLE TRUE
110 #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
111 #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY //DDR800_FREQUENCY
112 #define BLDCFG_DQS_TRAINING_CONTROL TRUE
113 #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
114 #define BLDCFG_USE_BURST_MODE FALSE
115 #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
116 #define BLDCFG_ENABLE_ECC_FEATURE TRUE
117 #define BLDCFG_ECC_REDIRECTION FALSE
118 #define BLDCFG_SCRUB_IC_RATE 0
119 #define BLDCFG_ECC_SYNC_FLOOD TRUE
120 #define BLDCFG_ECC_SYMBOL_SIZE 4
121
122 #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
123 #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
124
125 /**
126 * Enable Message Based C1e CPU feature in multi-socket systems.
127 * BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value,
128 * else the feature cannot be enabled.
129 */
130 #define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased
131 #define BLDCFG_PLATFORM_C1E_OPDATA 0x80//TODO
132 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
133 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
134
135 #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
136 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
137 #define BLDCFG_1GB_ALIGN FALSE
138 //#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
139 //#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
140 //
141
142 // Select the platform control flow mode for performance tuning.
143 #define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
144
145 /**
146 * Enable the probe filtering performance tuning feature.
147 * The probe filter provides filtering of broadcast probes to
148 * improve link bandwidth and performance for multi- node systems.
149 *
150 * This feature may interact with other performance features.
151 * TRUE -Enable the feature (default) if supported by all processors,
152 * based on revision and presence of L3 cache.
153 * The feature is not enabled if there are no coherent HT links.
154 * FALSE -Do not enable the feature regardless of the configuration.
155 */
156 //TODO enable it,
157 //but AGESA set PFMode = 0; //PF Disable, HW never set PFInitDone
158 //hang in F10HtAssistInit() do{...} while(PFInitDone != 1)
159 #define BLDCFG_USE_HT_ASSIST FALSE
160
161 /**
162 * The socket and link match values are platform specific
163 */
164 CONST MANUAL_BUID_SWAP_LIST ROMDATA s8226_manual_swaplist[2] =
165 {
166 {
167 /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
168 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
169
170 { //BUID Swap List
171 { //BUID Swaps
172 /* Each Non-coherent chain may have a list of device swaps,
173 * Each item specify a device will be swap from its current id to a new one
174 */
175 /* FromID 0x00 is the chain with the southbridge */
176 /* 'Move' device zero to device zero, All others are non applicable */
177 {0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
178 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
179 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
180 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
181 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
182 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
183 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
184 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
185 },
186
187 { //The ordered final BUIDs
188 /* Specify the final BUID to be zero, All others are non applicable */
189 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
190 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
191 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
192 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
193 }
194 }
195 },
196
197 /* The 2nd element in the array merely terminates the list */
198 {
199 HT_LIST_TERMINAL,
200 }
201 };
202
203 #define HYPERTRANSPORT_V31_SUPPORT 1
204
205 #if HYPERTRANSPORT_V31_SUPPORT
206 /**
207 * The socket and link match values are platform specific
208 *
209 */
210 CONST CPU_TO_CPU_PCB_LIMITS ROMDATA s8226_cpu2cpu_limit_list[2] =
211 {
212 {
213 /* On the reference platform, these settings apply to all coherent links */
214 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
215
216 /* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */
217 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
218 },
219
220 /* The 2nd element in the array merely terminates the list */
221 {
222 HT_LIST_TERMINAL,
223 }
224 };
225
226 CONST IO_PCB_LIMITS ROMDATA s8226_io_limit_list[2] =
227 {
228 {
229 /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
230 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
231
232 /* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */
233 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, //Actually IO hub only support 2600M MAX
234 },
235
236 /* The 2nd element in the array merely terminates the list */
237 {
238 HT_LIST_TERMINAL,
239 }
240 };
241 #else /* HYPERTRANSPORT_V31_SUPPORT == 0 */
242 CONST CPU_TO_CPU_PCB_LIMITS ROMDATA s8226_cpu2cpu_limit_list[2] =
243 {
244 {
245 /* On the reference platform, these settings apply to all coherent links */
246 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
247
248 /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
249 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
250 },
251
252 /* The 2nd element in the array merely terminates the list */
253 {
254 HT_LIST_TERMINAL,
255 }
256 };
257
258 CONST IO_PCB_LIMITS ROMDATA s8226_io_limit_list[2] =
259 {
260 {
261 /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
262 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
263
264 /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
265 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
266 },
267
268 /* The 2nd element in the array merely terminates the list */
269 {
270 HT_LIST_TERMINAL
271 }
272 };
273 #endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */
274
275 /**
276 * HyperTransport links will typically require an equalization at high frequencies.
277 * This is called deemphasis.
278 *
279 * Deemphasis is specified as levels, for example, -3 db.
280 * There are two levels for each link, its receiver deemphasis level and its DCV level,
281 * which is based on the far side transmitter's deemphasis.
282 * For each link, different levels may be required at each link frequency.
283 *
284 * Coherent connections between processors should have an entry for the port on each processor.
285 * There should be one entry for the host root port of each non-coherent chain.
286 *
287 * AGESA initialization code does not set deemphasis on IO Devices.
288 * A default is provided for internal links of MCM processors, and
289 * those links will generally not need deemphasis structures.
290 */
291 CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA s8226_deemphasis_list[] =
292 {
293 /* Socket, Link, LowFreq, HighFreq, Receiver Deemphasis, Dcv Deemphasis */
294
295 /* Non-coherent link deemphasis. */
296 {0, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
297 {0, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
298 {0, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
299 {0, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
300 {0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
301 {0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
302
303 {1, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
304 {1, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
305 {1, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
306 {1, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
307 {1, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
308 {1, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
309
310 {2, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
311 {2, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
312 {2, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
313 {2, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
314 {2, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
315 {2, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
316
317 {3, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
318 {3, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
319 {3, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
320 {3, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
321 {3, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
322 {3, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
323
324 /* Coherent link deemphasis. */
325 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
326 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3},
327 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus6},
328 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus6},
329 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus8},
330 {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2600M, HT_FREQUENCY_MAX, DeemphasisLevelMinus11pre8, DcvLevelMinus11},
331
332 /* End of the list */
333 {
334 HT_LIST_TERMINAL
335 }
336 };
337
338 /**
339 * For systems using socket infrastructure that permits strapping the SBI
340 * address for each socket, this should be used to provide a socket ID value.
341 * This is referred to as the hardware method for socket naming, and is the
342 * preferred solution.
343 */
344 /*
345 * I do NOT know howto config socket id in simnow,
346 * so use this software way to make HT works in simnow,
347 * real hardware do not need this Socket Map.
348 *
349 * A physical socket map for a 4 G34 Sockets MCM processors topology,
350 * reference the mainboard schemantic in detail.
351 *
352 */
353 CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA s8226_socket_map[] =
354 {
355 #define HT_SOCKET0 0
356 #define HT_SOCKET1 1
357 #define HT_SOCKET2 2
358 #define HT_SOCKET3 3
359
360 /**
361 * 0-3 are sublink 0, 4-7 are sublink 1
362 */
363 #define HT_LINK0A 0
364 #define HT_LINK1A 1
365 #define HT_LINK2A 2
366 #define HT_LINK3A 3
367 #define HT_LINK0B 4
368 #define HT_LINK1B 5
369 #define HT_LINK2B 6
370 #define HT_LINK3B 7
371
372 /* Source Socket, Link, Target Socket */
373 /* {HT_SOCKET0, HT_LINK0A, HT_SOCKET1},
374 {HT_SOCKET0, HT_LINK0B, HT_SOCKET3},
375 {HT_SOCKET0, HT_LINK1A, HT_SOCKET1},
376 {HT_SOCKET0, HT_LINK1B, HT_SOCKET3},
377 {HT_SOCKET0, HT_LINK3A, HT_SOCKET2},
378 {HT_SOCKET0, HT_LINK3B, HT_SOCKET2},
379
380 {HT_SOCKET1, HT_LINK0A, HT_SOCKET2},
381 {HT_SOCKET1, HT_LINK0B, HT_SOCKET3},
382 {HT_SOCKET1, HT_LINK1A, HT_SOCKET0},
383 {HT_SOCKET1, HT_LINK1B, HT_SOCKET2},
384 {HT_SOCKET1, HT_LINK3A, HT_SOCKET0},
385 {HT_SOCKET1, HT_LINK3B, HT_SOCKET3},
386
387 {HT_SOCKET2, HT_LINK0A, HT_SOCKET3},
388 {HT_SOCKET2, HT_LINK0B, HT_SOCKET0},
389 {HT_SOCKET2, HT_LINK1A, HT_SOCKET3},
390 {HT_SOCKET2, HT_LINK1B, HT_SOCKET1},
391 {HT_SOCKET2, HT_LINK3A, HT_SOCKET1},
392 {HT_SOCKET2, HT_LINK3B, HT_SOCKET0},
393
394 {HT_SOCKET3, HT_LINK0A, HT_SOCKET2},
395 {HT_SOCKET3, HT_LINK0B, HT_SOCKET1},
396 {HT_SOCKET3, HT_LINK1A, HT_SOCKET1},
397 {HT_SOCKET3, HT_LINK1B, HT_SOCKET0},
398 {HT_SOCKET3, HT_LINK3A, HT_SOCKET0},
399 {HT_SOCKET3, HT_LINK3B, HT_SOCKET2}, */
400 };
401
402 CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] =
403 {
404 {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E},
405 {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E},
406 {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000},
407 {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000},
408 {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000},
409 {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000},
410 {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000},
411 {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818},
412 {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818},
413 {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818},
414 {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818},
415 {CPU_LIST_TERMINAL}
416 };
417
418 #define BLDCFG_BUID_SWAP_LIST &s8226_manual_swaplist
419 #define BLDCFG_HTFABRIC_LIMITS_LIST &s8226_cpu2cpu_limit_list
420 #define BLDCFG_HTCHAIN_LIMITS_LIST &s8226_io_limit_list
421 #define BLDCFG_PLATFORM_DEEMPHASIS_LIST &s8226_deemphasis_list
422 #define BLDCFG_AP_MTRR_SETTINGS_LIST &s8226_ap_mtrr_list
423 //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &s8226_socket_map
424
425
426 /* Process the options...
427 * This file include MUST occur AFTER the user option selection settings
428 */
429 #define AGESA_ENTRY_INIT_RESET TRUE//FALSE
430 #define AGESA_ENTRY_INIT_RECOVERY FALSE
431 #define AGESA_ENTRY_INIT_EARLY TRUE
432 #define AGESA_ENTRY_INIT_POST TRUE
433 #define AGESA_ENTRY_INIT_ENV TRUE
434 #define AGESA_ENTRY_INIT_MID TRUE
435 #define AGESA_ENTRY_INIT_LATE TRUE
436 #define AGESA_ENTRY_INIT_S3SAVE TRUE
437 #define AGESA_ENTRY_INIT_RESUME TRUE
438 #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
439 #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
440
441 /*
442 #if CONFIG_CPU_AMD_AGESA_FAMILY15
443 #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
444 #endif
445 #if CONFIG_CPU_AMD_AGESA_FAMILY10
446 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
447 #endif
448 */
449
450 #include "SanMarinoInstall.h"
451
452 /*----------------------------------------------------------------------------------------
453 * CUSTOMER OVERIDES MEMORY TABLE
454 *----------------------------------------------------------------------------------------
455 */
456
457 //reference BKDG Table87: works
458 #define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
459 #define SEED_A 0x54
460 #define SEED_B 0x4D
461 #define SEED_C 0x45
462 #define SEED_D 0x40
463
464 #define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
465 //4B 41 51
466
467 /*
468 * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
469 * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
470 * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
471 * use its default conservative settings.
472 */
473 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
474 //
475 // The following macros are supported (use comma to separate macros):
476 //
477 // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
478 // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
479 // AGESA will base on this value to disable unused MemClk to save power.
480 // Example:
481 // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
482 // Bit AM3/S1g3 pin name
483 // 0 M[B,A]_CLK_H/L[0]
484 // 1 M[B,A]_CLK_H/L[1]
485 // 2 M[B,A]_CLK_H/L[2]
486 // 3 M[B,A]_CLK_H/L[3]
487 // 4 M[B,A]_CLK_H/L[4]
488 // 5 M[B,A]_CLK_H/L[5]
489 // 6 M[B,A]_CLK_H/L[6]
490 // 7 M[B,A]_CLK_H/L[7]
491 // And platform has the following routing:
492 // CS0 M[B,A]_CLK_H/L[4]
493 // CS1 M[B,A]_CLK_H/L[2]
494 // CS2 M[B,A]_CLK_H/L[3]
495 // CS3 M[B,A]_CLK_H/L[5]
496 // Then platform can specify the following macro:
497 // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
498 //
499 // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
500 // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
501 // AGESA will base on this value to tristate unused CKE to save power.
502 //
503 // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
504 // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
505 // AGESA will base on this value to tristate unused ODT pins to save power.
506 //
507 // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
508 // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
509 // AGESA will base on this value to tristate unused Chip select to save power.
510 //
511 // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
512 // Specifies the number of DIMM slots per channel.
513 //
514 // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
515 // Specifies the number of Chip selects per channel.
516 //
517 // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
518 // Specifies the number of channels per socket.
519 //
520 // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
521 // Specifies DDR bus speed of channel ChannelID on socket SocketID.
522 //
523 // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
524 // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
525 //
526 // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
527 // Byte6Seed, Byte7Seed, ByteEccSeed)
528 // Specifies the write leveling seed for a channel of a socket.
529 //
530
531 /* Specifies the write leveling seed for a channel of a socket.
532 * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID,
533 * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
534 * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed,
535 * ByteEccSeed)
536 */
537 WRITE_LEVELING_SEED(
538 ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
539 F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
540 F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
541 F15_WL_SEED),
542
543 /* HW_RXEN_SEED(SocketID, ChannelID, DimmID,
544 * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
545 * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed)
546 */
547 HW_RXEN_SEED(
548 ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
549 SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
550 SEED_A),
551 HW_RXEN_SEED(
552 ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
553 SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
554 SEED_B),
555 HW_RXEN_SEED(
556 ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
557 SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
558 SEED_C),
559 HW_RXEN_SEED(
560 ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
561 SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
562 SEED_D),
563
564 NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 3), //max 3
565 PSO_END
566 };
567
568 /*
569 * These tables are optional and may be used to adjust memory timing settings
570 */
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