src/mainboard/tyan/s2912_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #define FAM10_SCAN_PCI_BUS 0
  19 #define FAM10_ALLOCATE_IO_RANGE 1
  20
  21 #include <stdint.h>
  22 #include <string.h>
  23 #include <device/pci_def.h>
  24 #include <device/pci_ids.h>
  25 #include <arch/io.h>
  26 #include <device/pnp_def.h>
  27 #include <cpu/x86/lapic.h>
  28 #include <console/console.h>
  29 #include <timestamp.h>
  30 #include <lib.h>
  31 #include <spd.h>
  32 #include <cpu/amd/model_10xxx_rev.h>
  33 #include "southbridge/nvidia/mcp55/early_smbus.c"
  34 #include <northbridge/amd/amdfam10/raminit.h>
  35 #include <northbridge/amd/amdfam10/amdfam10.h>
  36 #include "lib/delay.c"
  37 #include <cpu/x86/lapic.h>
  38 #include "northbridge/amd/amdfam10/reset_test.c"
  39 #include <superio/winbond/common/winbond.h>
  40 #include <superio/winbond/w83627hf/w83627hf.h>
  41 #include <cpu/x86/bist.h>
  42 #include "northbridge/amd/amdfam10/debug.c"
  43 #include "northbridge/amd/amdfam10/setup_resource_map.c"
  44 #include "southbridge/nvidia/mcp55/early_ctrl.c"
  45
  46 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  47
  48 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  49
  50 static inline int spd_read_byte(unsigned device, unsigned address)
  51 {
  52         return smbus_read_byte(device, address);
  53 }
  54
  55 #include <northbridge/amd/amdfam10/amdfam10.h>
  56 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
  57 #include "northbridge/amd/amdfam10/pci.c"
  58 #include "resourcemap.c"
  59 #include "cpu/amd/quadcore/quadcore.c"
  60
  61 #define MCP55_MB_SETUP \
  62         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
  63         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
  64         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
  65         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
  66         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
  67         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
  68
  69 #include <southbridge/nvidia/mcp55/early_setup_ss.h>
  70 #include "southbridge/nvidia/mcp55/early_setup_car.c"
  71 #include <cpu/amd/microcode.h>
  72
  73 #include "cpu/amd/model_10xxx/init_cpus.c"
  74 #include "northbridge/amd/amdfam10/early_ht.c"
  75
  76 static void sio_setup(void)
  77 {
  78         uint32_t dword;
  79         uint8_t byte;
  80
  81         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
  82         byte |= 0x20;
  83         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
  84
  85         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
  86         /*serial 0 */
  87         dword |= (1<<0);
  88         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
  89
  90         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
  91         dword |= (1<<16);
  92         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
  93 }
  94
  95 static const u8 spd_addr[] = {
  96         //first node
  97         RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
  98 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  99         //second node
 100         RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
 101 #endif
 102 };
 103
 104 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 105 {
 106         struct sys_info *sysinfo = &sysinfo_car;
 107
 108         u32 bsp_apicid = 0, val, wants_reset;
 109         msr_t msr;
 110
 111         timestamp_init(timestamp_get());
 112         timestamp_add_now(TS_START_ROMSTAGE);
 113
 114         if (!cpu_init_detectedx && boot_cpu()) {
 115                 /* Nothing special needs to be done to find bus 0 */
 116                 /* Allow the HT devices to be found */
 117                 set_bsp_node_CHtExtNodeCfgEn();
 118                 enumerate_ht_chain();
 119                 sio_setup();
 120         }
 121
 122         post_code(0x30);
 123
 124         if (bist == 0)
 125                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 126
 127         post_code(0x32);
 128
 129         winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 130         console_init();
 131
 132         /* Halt if there was a built in self test failure */
 133         report_bist_failure(bist);
 134
 135         val = cpuid_eax(1);
 136         printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 137         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 138         printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
 139         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 140
 141         /* Setup sysinfo defaults */
 142         set_sysinfo_in_ram(0);
 143
 144         update_microcode(val);
 145
 146         post_code(0x33);
 147
 148         cpuSetAMDMSR();
 149         post_code(0x34);
 150
 151         amd_ht_init(sysinfo);
 152         post_code(0x35);
 153
 154         /* Setup nodes PCI space and start core 0 AP init. */
 155         finalize_node_setup(sysinfo);
 156
 157         /* Setup any mainboard PCI settings etc. */
 158         setup_mb_resource_map();
 159         post_code(0x36);
 160
 161         /* wait for all the APs core0 started by finalize_node_setup. */
 162         /* FIXME: A bunch of cores are going to start output to serial at once.
 163          * It would be nice to fixup prink spinlocks for ROM XIP mode.
 164          * I think it could be done by putting the spinlock flag in the cache
 165          * of the BSP located right after sysinfo.
 166          */
 167         wait_all_core0_started();
 168
 169 #if CONFIG_LOGICAL_CPUS
 170         /* Core0 on each node is configured. Now setup any additional cores. */
 171         printk(BIOS_DEBUG, "start_other_cores()\n");
 172         start_other_cores();
 173         post_code(0x37);
 174         wait_all_other_cores_started(bsp_apicid);
 175 #endif
 176
 177         post_code(0x38);
 178
 179 #if CONFIG_SET_FIDVID
 180         msr = rdmsr(0xc0010071);
 181         printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 182
 183         /* FIXME: The sb fid change may survive the warm reset and only
 184          * need to be done once.*/
 185         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 186
 187         post_code(0x39);
 188
 189         if (!warm_reset_detect(0)) {                    // BSP is node 0
 190                 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 191         } else {
 192                 init_fidvid_stage2(bsp_apicid, 0);      // BSP is node 0
 193         }
 194
 195         post_code(0x3A);
 196
 197         /* show final fid and vid */
 198         msr=rdmsr(0xc0010071);
 199         printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 200 #endif
 201
 202         init_timer(); // Need to use TMICT to synchronize FID/VID
 203
 204         wants_reset = mcp55_early_setup_x();
 205
 206         /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 207         if (!warm_reset_detect(0)) {
 208                 printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 209                 soft_reset();
 210                 die("After soft_reset_x - shouldn't see this message!!!\n");
 211         }
 212
 213         if (wants_reset)
 214                 printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
 215
 216         post_code(0x3B);
 217
 218         /* It's the time to set ctrl in sysinfo now; */
 219         printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 220         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 221         post_code(0x3D);
 222
 223         printk(BIOS_DEBUG, "enable_smbus()\n");
 224         enable_smbus();
 225
 226         post_code(0x40);
 227
 228         timestamp_add_now(TS_BEFORE_INITRAM);
 229         printk(BIOS_DEBUG, "raminit_amdmct()\n");
 230         raminit_amdmct(sysinfo);
 231         timestamp_add_now(TS_AFTER_INITRAM);
 232
 233         cbmem_initialize_empty();
 234         post_code(0x41);
 235
 236         amdmct_cbmem_store_info(sysinfo);
 237
 238         post_cache_as_ram();    // BSP switch stack to ram, copy then execute LB.
 239         post_code(0x43);        // Should never see this post code.
 240 }
 241
 242 /**
 243  * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
 244  * Description:
 245  *      This routine is called every time a non-coherent chain is processed.
 246  *      BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
 247  *      swap list. The first part of the list controls the BUID assignment and the
 248  *      second part of the list provides the device to device linking.  Device orientation
 249  *      can be detected automatically, or explicitly.  See documentation for more details.
 250  *
 251  *      Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
 252  *      based on each device's unit count.
 253  *
 254  * Parameters:
 255  *      @param[in]  node   = The node on which this chain is located
 256  *      @param[in]  link   = The link on the host for this chain
 257  *      @param[out] List   = supply a pointer to a list
 258  */
 259 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
 260 {
 261         static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
 262         /* If the BUID was adjusted in early_ht we need to do the manual override */
 263         if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
 264                 printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
 265                 if ((node == 0) && (link == 0)) {       /* BSP SB link */
 266                         *List = swaplist;
 267                         return 1;
 268                 }
 269         }
 270
 271         return 0;
 272 }