src/mainboard/technexion/tim8690/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <stdint.h>
  17 #include <string.h>
  18 #include <device/pci_def.h>
  19 #include <arch/io.h>
  20 #include <device/pnp_def.h>
  21 #include <cpu/x86/lapic.h>
  22 #include <pc80/mc146818rtc.h>
  23 #include <console/console.h>
  24 #include <cpu/amd/model_fxx_rev.h>
  25 #include <northbridge/amd/amdk8/raminit.h>
  26 #include <delay.h>
  27 #include <spd.h>
  28 #include <cpu/x86/lapic.h>
  29 #include "northbridge/amd/amdk8/reset_test.c"
  30 #include "northbridge/amd/amdk8/debug.c"
  31 #include <superio/ite/common/ite.h>
  32 #include <superio/ite/it8712f/it8712f.h>
  33 #include <cpu/x86/bist.h>
  34 #include "northbridge/amd/amdk8/setup_resource_map.c"
  35 #include "southbridge/amd/rs690/early_setup.c"
  36 #include "southbridge/amd/sb600/early_setup.c"
  37
  38 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
  39 #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
  40
  41 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  42 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  43
  44 static inline int spd_read_byte(u32 device, u32 address)
  45 {
  46         return smbus_read_byte(device, address);
  47 }
  48
  49 #include <northbridge/amd/amdk8/amdk8.h>
  50 #include "northbridge/amd/amdk8/incoherent_ht.c"
  51 #include "northbridge/amd/amdk8/raminit_f.c"
  52 #include "northbridge/amd/amdk8/coherent_ht.c"
  53 #include "lib/generic_sdram.c"
  54 #include "resourcemap.c"
  55 #include "cpu/amd/dualcore/dualcore.c"
  56 #include "cpu/amd/model_fxx/init_cpus.c"
  57 #include "cpu/amd/model_fxx/fidvid.c"
  58 #include "northbridge/amd/amdk8/early_ht.c"
  59
  60 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  61 {
  62         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
  63         int needs_reset = 0;
  64         u32 bsp_apicid = 0;
  65         msr_t msr;
  66         struct cpuid_result cpuid1;
  67         struct sys_info *sysinfo = &sysinfo_car;
  68
  69         if (!cpu_init_detectedx && boot_cpu()) {
  70                 /* Nothing special needs to be done to find bus 0 */
  71                 /* Allow the HT devices to be found */
  72                 enumerate_ht_chain();
  73                 /* sb600_lpc_port80(); */
  74                 sb600_pci_port80();
  75         }
  76
  77         if (bist == 0)
  78                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
  79
  80         enable_rs690_dev8();
  81         sb600_lpc_init();
  82
  83         ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  84         ite_kill_watchdog(GPIO_DEV);
  85
  86         console_init();
  87
  88         /* Halt if there was a built in self test failure */
  89         report_bist_failure(bist);
  90         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
  91
  92         setup_tim8690_resource_map();
  93
  94         setup_coherent_ht_domain();
  95
  96 #if CONFIG_LOGICAL_CPUS
  97         /* It is said that we should start core1 after all core0 launched */
  98         wait_all_core0_started();
  99         start_other_cores();
 100 #endif
 101         wait_all_aps_started(bsp_apicid);
 102
 103         ht_setup_chains_x(sysinfo);
 104
 105         /* run _early_setup before soft-reset. */
 106         rs690_early_setup();
 107         sb600_early_setup();
 108
 109         /* Check to see if processor is capable of changing FIDVID  */
 110         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 111         cpuid1 = cpuid(0x80000007);
 112         if ((cpuid1.edx & 0x6) == 0x6 ) {
 113                 /* Read FIDVID_STATUS */
 114                 msr=rdmsr(0xc0010042);
 115                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 116
 117                 enable_fid_change();
 118                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 119                 init_fidvid_bsp(bsp_apicid);
 120
 121                 /* show final fid and vid */
 122                 msr=rdmsr(0xc0010042);
 123                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 124         } else {
 125                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 126         }
 127
 128         needs_reset = optimize_link_coherent_ht();
 129         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 130         rs690_htinit();
 131         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 132
 133         if (needs_reset) {
 134                 printk(BIOS_INFO, "ht reset -\n");
 135                 soft_reset();
 136         }
 137
 138         allow_all_aps_stop(bsp_apicid);
 139
 140         /* It's the time to set ctrl now; */
 141         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 142                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 143         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 144         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 145
 146         rs690_before_pci_init();
 147         sb600_before_pci_init();
 148
 149         post_cache_as_ram();
 150 }