src/mainboard/supermicro/h8scm_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 //#define SYSTEM_TYPE 0 /* SERVER */ //FIXME SERVER enable ECC, cause linux hang
  17 #define SYSTEM_TYPE 1   /* DESKTOP */
  18 //#define SYSTEM_TYPE 2 /* MOBILE */
  19
  20 //used by incoherent_ht
  21 #define FAM10_SCAN_PCI_BUS 0
  22 #define FAM10_ALLOCATE_IO_RANGE 0
  23
  24 #include <stdint.h>
  25 #include <string.h>
  26 #include <device/pci_def.h>
  27 #include <device/pci_ids.h>
  28 #include <arch/io.h>
  29 #include <device/pnp_def.h>
  30 #include <cpu/x86/lapic.h>
  31 #include <console/console.h>
  32 #include <timestamp.h>
  33 #include <cpu/amd/model_10xxx_rev.h>
  34 #include <northbridge/amd/amdfam10/raminit.h>
  35 #include <northbridge/amd/amdfam10/amdfam10.h>
  36 #include <lib.h>
  37 #include <cpu/x86/lapic.h>
  38 #include "northbridge/amd/amdfam10/reset_test.c"
  39 #include <commonlib/loglevel.h>
  40 #include <cpu/x86/bist.h>
  41 #include <cpu/amd/mtrr.h>
  42 #include "northbridge/amd/amdfam10/setup_resource_map.c"
  43 #include <southbridge/amd/sb700/sb700.h>
  44 #include <southbridge/amd/sb700/smbus.h>
  45 #include <southbridge/amd/sr5650/sr5650.h>
  46 #include <superio/nuvoton/wpcm450/wpcm450.h>
  47 #include "northbridge/amd/amdfam10/debug.c"
  48
  49 static void activate_spd_rom(const struct mem_controller *ctrl)
  50 {
  51 }
  52
  53 static int spd_read_byte(u32 device, u32 address)
  54 {
  55         return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
  56 }
  57
  58 #include <northbridge/amd/amdfam10/amdfam10.h>
  59 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
  60 #include "northbridge/amd/amdfam10/pci.c"
  61 #include "resourcemap.c"
  62 #include "cpu/amd/quadcore/quadcore.c"
  63 #include <cpu/amd/microcode.h>
  64 #include "cpu/amd/model_10xxx/init_cpus.c"
  65 #include "northbridge/amd/amdfam10/early_ht.c"
  66 #include <spd.h>
  67
  68 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  69 {
  70         struct sys_info *sysinfo = &sysinfo_car;
  71         static const u8 spd_addr[] = {
  72                                 RC00, 0x52,  0x53,  0, 0, 0x50,  0x51,  0, 0,
  73                                 //RC00, DIMM2, DIMM3, 0, 0, DIMM0, DIMM1, 0, 0,
  74                         };
  75         u32 bsp_apicid = 0;
  76         u32 val;
  77         msr_t msr;
  78
  79         timestamp_init(timestamp_get());
  80         timestamp_add_now(TS_START_ROMSTAGE);
  81
  82         if (!cpu_init_detectedx && boot_cpu()) {
  83                 /* Nothing special needs to be done to find bus 0 */
  84                 /* Allow the HT devices to be found */
  85                 /* mov bsp to bus 0xff when > 8 nodes */
  86                 set_bsp_node_CHtExtNodeCfgEn();
  87                 enumerate_ht_chain();
  88
  89                 /* SR56x0 pcie bridges block pci_locate_device() before pcie training.
  90                  * disable all pcie bridges on SR56x0 to work around it
  91                  */
  92                 sr5650_disable_pcie_bridge();
  93                 sb7xx_51xx_lpc_port80();
  94         }
  95
  96         post_code(0x30);
  97
  98         if (bist == 0) {
  99                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
 100                 /* All cores run this but the BSP(node0,core0) is the only core that returns. */
 101         }
 102
 103         post_code(0x32);
 104
 105         enable_sr5650_dev8();
 106         sb7xx_51xx_lpc_init();
 107
 108         sb7xx_51xx_enable_wideio(0, 0x1600);
 109
 110         wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE);
 111
 112         sb7xx_51xx_disable_wideio(0);
 113
 114         console_init();
 115
 116 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 117
 118         /* Halt if there was a built in self test failure */
 119         report_bist_failure(bist);
 120
 121         // Load MPB
 122         val = cpuid_eax(1);
 123         printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 124         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 125         printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
 126         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 127
 128         /* Setup sysinfo defaults */
 129         set_sysinfo_in_ram(0);
 130
 131         update_microcode(val);
 132
 133         post_code(0x33);
 134
 135         cpuSetAMDMSR();
 136         post_code(0x34);
 137
 138         /* TODO: The Kernel must support 12 processor, otherwise the interrupt
 139          * can not work correctly. */
 140         amd_ht_init(sysinfo);
 141         post_code(0x35);
 142
 143         /* Setup nodes PCI space and start core 0 AP init. */
 144         finalize_node_setup(sysinfo);
 145
 146         /* Setup any mainboard PCI settings etc. */
 147         setup_mb_resource_map();
 148         post_code(0x36);
 149
 150         /* wait for all the APs core0 started by finalize_node_setup. */
 151         /* FIXME: A bunch of cores are going to start output to serial at once.
 152            It would be nice to fixup prink spinlocks for ROM XIP mode.
 153            I think it could be done by putting the spinlock flag in the cache
 154            of the BSP located right after sysinfo.
 155          */
 156         wait_all_core0_started();
 157
 158 #if CONFIG_LOGICAL_CPUS
 159         /* Core0 on each node is configured. Now setup any additional cores. */
 160         printk(BIOS_DEBUG, "start_other_cores()\n");
 161         start_other_cores();
 162         post_code(0x37);
 163         wait_all_other_cores_started(bsp_apicid);
 164 #endif
 165
 166         post_code(0x38);
 167
 168         /* run _early_setup before soft-reset. */
 169         sr5650_early_setup();
 170         sb7xx_51xx_early_setup();
 171
 172 #if CONFIG_SET_FIDVID
 173         msr = rdmsr(0xc0010071);
 174         printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 175
 176         /* FIXME: The sb fid change may survive the warm reset and only
 177            need to be done once.*/
 178         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 179
 180         post_code(0x39);
 181
 182         if (!warm_reset_detect(0)) {                    // BSP is node 0
 183                 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 184         } else {
 185                 init_fidvid_stage2(bsp_apicid, 0);      // BSP is node 0
 186         }
 187
 188         post_code(0x3A);
 189
 190         /* show final fid and vid */
 191         msr=rdmsr(0xc0010071);
 192         printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 193 #endif
 194
 195         sr5650_htinit();
 196
 197         /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 198         if (!warm_reset_detect(0)) {
 199                 printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 200                 soft_reset();
 201                 die("After soft_reset_x - shouldn't see this message!!!\n");
 202         }
 203
 204         post_code(0x3B);
 205
 206         /* It's the time to set ctrl in sysinfo now; */
 207         printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 208         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 209
 210         post_code(0x40);
 211
 212
 213         timestamp_add_now(TS_BEFORE_INITRAM);
 214         printk(BIOS_DEBUG, "raminit_amdmct()\n");
 215         raminit_amdmct(sysinfo);
 216         timestamp_add_now(TS_AFTER_INITRAM);
 217
 218         cbmem_initialize_empty();
 219         post_code(0x41);
 220
 221         amdmct_cbmem_store_info(sysinfo);
 222
 223 /*
 224         dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
 225         dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
 226         dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
 227         dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
 228 */
 229
 230 //      ram_check(0x00200000, 0x00200000 + (640 * 1024));
 231 //      ram_check(0x40200000, 0x40200000 + (640 * 1024));
 232
 233 //      die("After MCT init before CAR disabled.");
 234
 235         sr5650_before_pci_init();
 236         sb7xx_51xx_before_pci_init();
 237
 238         post_code(0x42);
 239         post_cache_as_ram();    // BSP switch stack to ram, copy then execute LB.
 240         post_code(0x43);        // Should never see this post code.
 241 }
 242
 243 /**
 244  * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
 245  * Description:
 246  *      This routine is called every time a non-coherent chain is processed.
 247  *      BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
 248  *      swap list. The first part of the list controls the BUID assignment and the
 249  *      second part of the list provides the device to device linking.  Device orientation
 250  *      can be detected automatically, or explicitly.  See documentation for more details.
 251  *
 252  *      Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
 253  *      based on each device's unit count.
 254  *
 255  * Parameters:
 256  *      @param[in]  node   = The node on which this chain is located
 257  *      @param[in]  link   = The link on the host for this chain
 258  *      @param[out] List   = supply a pointer to a list
 259  */
 260 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
 261 {
 262         static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
 263         /* If the BUID was adjusted in early_ht we need to do the manual override */
 264         if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
 265                 printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
 266                 if ((node == 0) && (link == 0)) {       /* BSP SB link */
 267                         *List = swaplist;
 268                         return 1;
 269                 }
 270         }
 271
 272         return 0;
 273 }