src/mainboard/supermicro/h8scm/sb700_cfg.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16
  17 #ifndef _SB700_CFG_H_
  18 #define _SB700_CFG_H_
  19
  20 #include <stdint.h>
  21
  22
  23 /**
  24  * @def BIOS_SIZE_1M
  25  * @def BIOS_SIZE_2M
  26  * @def BIOS_SIZE_4M
  27  * @def BIOS_SIZE_8M
  28  */
  29 #define BIOS_SIZE_1M                    0
  30 #define BIOS_SIZE_2M                    1
  31 #define BIOS_SIZE_4M                    3
  32 #define BIOS_SIZE_8M                    7
  33
  34 /* In SB700, default ROM size is 1M Bytes, if your platform ROM
  35  * bigger than 1M you have to set the ROM size outside CIMx module and
  36  * before AGESA module get call.
  37  */
  38 #ifndef BIOS_SIZE
  39 #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
  40 #define BIOS_SIZE BIOS_SIZE_1M
  41 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
  42 #define BIOS_SIZE BIOS_SIZE_2M
  43 #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
  44 #define BIOS_SIZE BIOS_SIZE_4M
  45 #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
  46 #define BIOS_SIZE BIOS_SIZE_8M
  47 #endif
  48 #endif
  49
  50 /**
  51  * @def SPREAD_SPECTRUM
  52  * @brief
  53  *  0 - Disable Spread Spectrum function
  54  *  1 - Enable  Spread Spectrum function
  55  */
  56 #define SPREAD_SPECTRUM                 0
  57
  58 /**
  59  * @def SB_HPET_TIMER
  60  * @brief
  61  *  0 - Disable hpet
  62  *  1 - Enable  hpet
  63  */
  64 #define HPET_TIMER                      1
  65
  66 /**
  67  * @def USB_CONFIG
  68  * @brief bit[0-6] used to control USB
  69  *   0 - Disable
  70  *   1 - Enable
  71  *  Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
  72  *  Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
  73  *  Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
  74  *  Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
  75  *  Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
  76  *  Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
  77  *  Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
  78  */
  79 #define USB_CINFIG              0x7F
  80
  81 /**
  82  * @def PCI_CLOCK_CTRL
  83  * @brief bit[0-4] used for PCI Slots Clock Control,
  84  *   0 - disable
  85  *   1 - enable
  86  *  PCI SLOT 0 define at BIT0
  87  *  PCI SLOT 1 define at BIT1
  88  *  PCI SLOT 2 define at BIT2
  89  *  PCI SLOT 3 define at BIT3
  90  *  PCI SLOT 4 define at BIT4
  91  */
  92 #define PCI_CLOCK_CTRL                  0x1F
  93
  94 /**
  95  * @def SATA_CONTROLLER
  96  * @brief INCHIP Sata Controller
  97  */
  98 #ifndef SATA_CONTROLLER
  99 #define SATA_CONTROLLER               1
 100 #endif
 101
 102 /**
 103  * @def SATA_MODE
 104  * @brief INCHIP Sata Controller Mode
 105  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
 106  */
 107 #ifndef SATA_MODE
 108 #define SATA_MODE                     NATIVE_IDE_MODE
 109 #endif
 110
 111 /**
 112  * @brief INCHIP Sata IDE Controller Mode
 113  */
 114 #define IDE_LEGACY_MODE                 0
 115 #define IDE_NATIVE_MODE                 1
 116
 117 /**
 118  * @def SATA_IDE_MODE
 119  * @brief INCHIP Sata IDE Controller Mode
 120  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
 121  */
 122 #ifndef SATA_IDE_MODE
 123 #define SATA_IDE_MODE                 IDE_LEGACY_MODE
 124 #endif
 125
 126 /**
 127  * @def EXTERNAL_CLOCK
 128  * @brief 00/10: Reference clock from crystal oscillator via
 129  *  PAD_XTALI and PAD_XTALO
 130  *
 131  * @def INTERNAL_CLOCK
 132  * @brief 01/11: Reference clock from internal clock through
 133  *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
 134  */
 135 #define EXTERNAL_CLOCK          0x00
 136 #define INTERNAL_CLOCK          0x01
 137
 138 #define SATA_CLOCK_SOURCE       EXTERNAL_CLOCK
 139
 140 /**
 141  * @def SATA_PORT_MULT_CAP_RESERVED
 142  * @brief 1 ON, 0 0FF
 143  */
 144 #define SATA_PORT_MULT_CAP_RESERVED     1
 145
 146
 147 /**
 148  * @def   AZALIA_AUTO
 149  * @brief Detect Azalia controller automatically.
 150  *
 151  * @def   AZALIA_DISABLE
 152  * @brief Disable Azalia controller.
 153
 154  * @def   AZALIA_ENABLE
 155  * @brief Enable Azalia controller.
 156  */
 157 #define AZALIA_AUTO                     0
 158 #define AZALIA_DISABLE                  1
 159 #define AZALIA_ENABLE                   2
 160
 161 /**
 162  * @brief INCHIP HDA controller
 163  */
 164 #ifndef AZALIA_CONTROLLER
 165 #define AZALIA_CONTROLLER             AZALIA_AUTO
 166 #endif
 167
 168 /**
 169  * @def AZALIA_PIN_CONFIG
 170  * @brief
 171  *  0 - disable
 172  *  1 - enable
 173  */
 174 #ifndef AZALIA_PIN_CONFIG
 175 #define AZALIA_PIN_CONFIG             1
 176 #endif
 177
 178 /**
 179  * @def AZALIA_SDIN_PIN
 180  * @brief
 181  *  SDIN0 is define at BIT0 & BIT1
 182  *   00 - GPIO PIN
 183  *   01 - Reserved
 184  *   10 - As a Azalia SDIN pin
 185  *  SDIN1 is define at BIT2 & BIT3
 186  *  SDIN2 is define at BIT4 & BIT5
 187  *  SDIN3 is define at BIT6 & BIT7
 188  */
 189 #ifndef AZALIA_SDIN_PIN
 190 //#define AZALIA_SDIN_PIN             0xAA
 191 #define AZALIA_SDIN_PIN
 192 #define AZALIA_SDIN_PIN_0             0x2
 193 #define AZALIA_SDIN_PIN_1             0x2
 194 #define AZALIA_SDIN_PIN_2             0x2
 195 #define AZALIA_SDIN_PIN_3             0x0
 196 #endif
 197
 198 /**
 199  * @def GPP_CONTROLLER
 200  */
 201 #ifndef GPP_CONTROLLER
 202 #define GPP_CONTROLLER                1
 203 #endif
 204
 205 /**
 206  * @def GPP_CFGMODE
 207  * @brief GPP Link Configuration
 208  * four possible configuration:
 209  *  GPP_CFGMODE_X4000
 210  *  GPP_CFGMODE_X2200
 211  *  GPP_CFGMODE_X2110
 212  *  GPP_CFGMODE_X1111
 213  */
 214 #ifndef GPP_CFGMODE
 215 #define GPP_CFGMODE                   GPP_CFGMODE_X1111
 216 #endif
 217
 218
 219 /**
 220  * @brief South Bridge CIMx configuration
 221  *
 222  */
 223 void sb700_cimx_config(AMDSBCFG *sb_cfg);
 224
 225 /**
 226  * @brief Entry point of Southbridge CIMx callout
 227  *
 228  * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
 229  *
 230  * @param[in] func    Southbridge CIMx Function ID.
 231  * @param[in] data    Southbridge Input Data.
 232  * @param[in] config  Southbridge configuration structure pointer.
 233  *
 234  */
 235 u32 sb700_callout_entry(u32 func, u32 data, void* config);
 236
 237 #endif //_SB700_CFG_H_