| blob | 4c49e92872fe63922102c7ee58eace22d571e8ca |
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
16 /* DefinitionBlock Statement */
17 DefinitionBlock (
18 "DSDT.AML", /* Output filename */
19 "DSDT", /* Signature */
20 0x02, /* DSDT Revision, needs to be 2 for 64bit */
21 "AMD ", /* OEMID */
22 "COREBOOT", /* TABLE ID */
23 0x00010001 /* OEM Revision */
24 )
25 { /* Start of ASL file */
26 /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
28 /* Data to be patched by the BIOS during POST */
29 /* FIXME the patching is not done yet! */
30 /* Memory related values */
31 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
32 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
33 Name(PBLN, 0x0) /* Length of BIOS area */
35 Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
36 Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
38 Name(HPBA, 0xFED00000) /* Base address of HPET table */
39 Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
41 /* USB overcurrent mapping pins. */
42 Name(UOM0, 0)
43 Name(UOM1, 2)
44 Name(UOM2, 0)
45 Name(UOM3, 7)
46 Name(UOM4, 2)
47 Name(UOM5, 2)
48 Name(UOM6, 6)
49 Name(UOM7, 2)
50 Name(UOM8, 6)
51 Name(UOM9, 6)
53 /* Some global data */
54 Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
55 Name(OSV, Ones) /* Assume nothing */
56 Name(PMOD, One) /* Assume APIC */
58 /*
59 * Processor Object
60 *
61 */
62 Scope (\_PR) { /* define processor scope */
63 Processor(
64 C000, /* name space name */
65 0x00, /* Unique number for this processor */
66 0x810, /* PBLK system I/O address !hardcoded! */
67 0x06 /* PBLKLEN for boot processor */
68 ) {
69 //#include "acpi/cpstate.asl"
70 }
71 Processor(C001, 0x01, 0x00000000, 0x00) {}
72 Processor(C002, 0x02, 0x00000000, 0x00) {}
73 Processor(C003, 0x03, 0x00000000, 0x00) {}
74 Processor(C004, 0x04, 0x00000000, 0x00) {}
75 Processor(C005, 0x05, 0x00000000, 0x00) {}
76 Processor(C006, 0x06, 0x00000000, 0x00) {}
77 Processor(C007, 0x07, 0x00000000, 0x00) {}
78 Processor(C008, 0x08, 0x00000000, 0x00) {}
79 Processor(C009, 0x09, 0x00000000, 0x00) {}
80 Processor(C00A, 0x0A, 0x00000000, 0x00) {}
81 Processor(C00B, 0x0B, 0x00000000, 0x00) {}
82 Processor(C00C, 0x0C, 0x00000000, 0x00) {}
83 Processor(C00D, 0x0D, 0x00000000, 0x00) {}
84 Processor(C00E, 0x0E, 0x00000000, 0x00) {}
85 Processor(C00F, 0x0F, 0x00000000, 0x00) {}
86 Processor(C010, 0x10, 0x00000000, 0x00) {}
87 Processor(C011, 0x11, 0x00000000, 0x00) {}
88 Processor(C012, 0x12, 0x00000000, 0x00) {}
89 Processor(C013, 0x13, 0x00000000, 0x00) {}
90 Processor(C014, 0x14, 0x00000000, 0x00) {}
91 Processor(C015, 0x15, 0x00000000, 0x00) {}
92 Processor(C016, 0x16, 0x00000000, 0x00) {}
93 Processor(C017, 0x17, 0x00000000, 0x00) {}
94 Processor(C018, 0x18, 0x00000000, 0x00) {}
95 Processor(C019, 0x19, 0x00000000, 0x00) {}
96 Processor(C01A, 0x1A, 0x00000000, 0x00) {}
97 Processor(C01B, 0x1B, 0x00000000, 0x00) {}
98 Processor(C01C, 0x1C, 0x00000000, 0x00) {}
99 Processor(C01D, 0x1D, 0x00000000, 0x00) {}
100 Processor(C01E, 0x1E, 0x00000000, 0x00) {}
101 Processor(C01F, 0x1F, 0x00000000, 0x00) {}
102 Processor(C020, 0x20, 0x00000000, 0x00) {}
103 Processor(C021, 0x21, 0x00000000, 0x00) {}
104 Processor(C022, 0x22, 0x00000000, 0x00) {}
105 Processor(C023, 0x23, 0x00000000, 0x00) {}
106 Processor(C024, 0x24, 0x00000000, 0x00) {}
107 Processor(C025, 0x25, 0x00000000, 0x00) {}
108 Processor(C026, 0x26, 0x00000000, 0x00) {}
109 Processor(C027, 0x27, 0x00000000, 0x00) {}
110 Processor(C028, 0x28, 0x00000000, 0x00) {}
111 Processor(C029, 0x29, 0x00000000, 0x00) {}
112 Processor(C02A, 0x2A, 0x00000000, 0x00) {}
113 Processor(C02B, 0x2B, 0x00000000, 0x00) {}
114 Processor(C02C, 0x2C, 0x00000000, 0x00) {}
115 Processor(C02D, 0x2D, 0x00000000, 0x00) {}
116 Processor(C02E, 0x2E, 0x00000000, 0x00) {}
117 Processor(C02F, 0x2F, 0x00000000, 0x00) {}
118 Alias (C000, CPU0)
119 Alias (C001, CPU1)
120 Alias (C002, CPU2)
121 Alias (C003, CPU3)
122 Alias (C004, CPU4)
123 Alias (C005, CPU5)
124 Alias (C006, CPU6)
125 Alias (C007, CPU7)
126 Alias (C008, CPU8)
127 } /* End _PR scope */
129 /* PIC IRQ mapping registers, C00h-C01h */
130 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
131 Field(PRQM, ByteAcc, NoLock, Preserve) {
132 PRQI, 0x00000008,
133 PRQD, 0x00000008, /* Offset: 1h */
134 }
135 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
136 PINA, 0x00000008, /* Index 0 */
137 PINB, 0x00000008, /* Index 1 */
138 PINC, 0x00000008, /* Index 2 */
139 PIND, 0x00000008, /* Index 3 */
140 AINT, 0x00000008, /* Index 4 */
141 SINT, 0x00000008, /* Index 5 */
142 , 0x00000008, /* Index 6 */
143 AAUD, 0x00000008, /* Index 7 */
144 AMOD, 0x00000008, /* Index 8 */
145 PINE, 0x00000008, /* Index 9 */
146 PINF, 0x00000008, /* Index A */
147 PING, 0x00000008, /* Index B */
148 PINH, 0x00000008, /* Index C */
149 }
151 /* PCI Error control register */
152 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
153 Field(PERC, ByteAcc, NoLock, Preserve) {
154 SENS, 0x00000001,
155 PENS, 0x00000001,
156 SENE, 0x00000001,
157 PENE, 0x00000001,
158 }
160 /* Client Management index/data registers */
161 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
162 Field(CMT, ByteAcc, NoLock, Preserve) {
163 CMTI, 8,
164 /* Client Management Data register */
165 G64E, 1,
166 G64O, 1,
167 G32O, 2,
168 , 2,
169 GPSL, 2,
170 }
172 /* GPM Port register */
173 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
174 Field(GPT, ByteAcc, NoLock, Preserve) {
175 GPB0,1,
176 GPB1,1,
177 GPB2,1,
178 GPB3,1,
179 GPB4,1,
180 GPB5,1,
181 GPB6,1,
182 GPB7,1,
183 }
185 /* Flash ROM program enable register */
186 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
187 Field(FRE, ByteAcc, NoLock, Preserve) {
188 , 0x00000006,
189 FLRE, 0x00000001,
190 }
192 /* PM2 index/data registers */
193 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
194 Field(PM2R, ByteAcc, NoLock, Preserve) {
195 PM2I, 0x00000008,
196 PM2D, 0x00000008,
197 }
199 /* Power Management I/O registers */
200 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
201 Field(PIOR, ByteAcc, NoLock, Preserve) {
202 PIOI, 0x00000008,
203 PIOD, 0x00000008,
204 }
205 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
206 Offset(0x00), /* MiscControl */
207 , 1,
208 T1EE, 1,
209 T2EE, 1,
210 Offset(0x01), /* MiscStatus */
211 , 1,
212 T1E, 1,
213 T2E, 1,
214 Offset(0x04), /* SmiWakeUpEventEnable3 */
215 , 7,
216 SSEN, 1,
217 Offset(0x07), /* SmiWakeUpEventStatus3 */
218 , 7,
219 CSSM, 1,
220 Offset(0x10), /* AcpiEnable */
221 , 6,
222 PWDE, 1,
223 Offset(0x1C), /* ProgramIoEnable */
224 , 3,
225 MKME, 1,
226 IO3E, 1,
227 IO2E, 1,
228 IO1E, 1,
229 IO0E, 1,
230 Offset(0x1D), /* IOMonitorStatus */
231 , 3,
232 MKMS, 1,
233 IO3S, 1,
234 IO2S, 1,
235 IO1S, 1,
236 IO0S,1,
237 Offset(0x20), /* AcpiPmEvtBlk */
238 APEB, 16,
239 Offset(0x36), /* GEvtLevelConfig */
240 , 6,
241 ELC6, 1,
242 ELC7, 1,
243 Offset(0x37), /* GPMLevelConfig0 */
244 , 3,
245 PLC0, 1,
246 PLC1, 1,
247 PLC2, 1,
248 PLC3, 1,
249 PLC8, 1,
250 Offset(0x38), /* GPMLevelConfig1 */
251 , 1,
252 PLC4, 1,
253 PLC5, 1,
254 , 1,
255 PLC6, 1,
256 PLC7, 1,
257 Offset(0x3B), /* PMEStatus1 */
258 GP0S, 1,
259 GM4S, 1,
260 GM5S, 1,
261 APS, 1,
262 GM6S, 1,
263 GM7S, 1,
264 GP2S, 1,
265 STSS, 1,
266 Offset(0x55), /* SoftPciRst */
267 SPRE, 1,
268 , 1,
269 , 1,
270 PNAT, 1,
271 PWMK, 1,
272 PWNS, 1,
274 /* Offset(0x61), */ /* Options_1 */
275 /* ,7, */
276 /* R617,1, */
278 Offset(0x65), /* UsbPMControl */
279 , 4,
280 URRE, 1,
281 Offset(0x68), /* MiscEnable68 */
282 , 3,
283 TMTE, 1,
284 , 1,
285 Offset(0x92), /* GEVENTIN */
286 , 7,
287 E7IS, 1,
288 Offset(0x96), /* GPM98IN */
289 G8IS, 1,
290 G9IS, 1,
291 Offset(0x9A), /* EnhanceControl */
292 ,7,
293 HPDE, 1,
294 Offset(0xA8), /* PIO7654Enable */
295 IO4E, 1,
296 IO5E, 1,
297 IO6E, 1,
298 IO7E, 1,
299 Offset(0xA9), /* PIO7654Status */
300 IO4S, 1,
301 IO5S, 1,
302 IO6S, 1,
303 IO7S, 1,
304 }
306 /* PM1 Event Block
307 * First word is PM1_Status, Second word is PM1_Enable
308 */
309 OperationRegion(P1EB, SystemIO, APEB, 0x04)
310 Field(P1EB, ByteAcc, NoLock, Preserve) {
311 TMST, 1,
312 , 3,
313 BMST, 1,
314 GBST, 1,
315 Offset(0x01),
316 PBST, 1,
317 , 1,
318 RTST, 1,
319 , 3,
320 PWST, 1,
321 SPWS, 1,
322 Offset(0x02),
323 TMEN, 1,
324 , 4,
325 GBEN, 1,
326 Offset(0x03),
327 PBEN, 1,
328 , 1,
329 RTEN, 1,
330 , 3,
331 PWDA, 1,
332 }
334 OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
335 Field (GRAM, ByteAcc, Lock, Preserve)
336 {
337 Offset (0x10),
338 FLG0, 8
339 }
341 Scope(\_SB) {
342 /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
343 OperationRegion(PCFG, SystemMemory, PCBA, PCLN)
344 Field(PCFG, ByteAcc, NoLock, Preserve) {
345 /* Byte offsets are computed using the following technique:
346 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
347 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
348 */
349 Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
350 STB5, 32,
351 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
352 PT0D, 1,
353 PT1D, 1,
354 PT2D, 1,
355 PT3D, 1,
356 PT4D, 1,
357 PT5D, 1,
358 PT6D, 1,
359 PT7D, 1,
360 PT8D, 1,
361 PT9D, 1,
362 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
363 SBIE, 1,
364 SBME, 1,
365 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
366 SBRI, 8,
367 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
368 SBB1, 32,
369 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
370 ,14,
371 P92E, 1, /* Port92 decode enable */
372 }
374 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
375 Field(SB5, AnyAcc, NoLock, Preserve){
376 /* Port 0 */
377 Offset(0x120), /* Port 0 Task file status */
378 P0ER, 1,
379 , 2,
380 P0DQ, 1,
381 , 3,
382 P0BY, 1,
383 Offset(0x128), /* Port 0 Serial ATA status */
384 P0DD, 4,
385 , 4,
386 P0IS, 4,
387 Offset(0x12C), /* Port 0 Serial ATA control */
388 P0DI, 4,
389 Offset(0x130), /* Port 0 Serial ATA error */
390 , 16,
391 P0PR, 1,
393 /* Port 1 */
394 offset(0x1A0), /* Port 1 Task file status */
395 P1ER, 1,
396 , 2,
397 P1DQ, 1,
398 , 3,
399 P1BY, 1,
400 Offset(0x1A8), /* Port 1 Serial ATA status */
401 P1DD, 4,
402 , 4,
403 P1IS, 4,
404 Offset(0x1AC), /* Port 1 Serial ATA control */
405 P1DI, 4,
406 Offset(0x1B0), /* Port 1 Serial ATA error */
407 , 16,
408 P1PR, 1,
410 /* Port 2 */
411 Offset(0x220), /* Port 2 Task file status */
412 P2ER, 1,
413 , 2,
414 P2DQ, 1,
415 , 3,
416 P2BY, 1,
417 Offset(0x228), /* Port 2 Serial ATA status */
418 P2DD, 4,
419 , 4,
420 P2IS, 4,
421 Offset(0x22C), /* Port 2 Serial ATA control */
422 P2DI, 4,
423 Offset(0x230), /* Port 2 Serial ATA error */
424 , 16,
425 P2PR, 1,
427 /* Port 3 */
428 Offset(0x2A0), /* Port 3 Task file status */
429 P3ER, 1,
430 , 2,
431 P3DQ, 1,
432 , 3,
433 P3BY, 1,
434 Offset(0x2A8), /* Port 3 Serial ATA status */
435 P3DD, 4,
436 , 4,
437 P3IS, 4,
438 Offset(0x2AC), /* Port 3 Serial ATA control */
439 P3DI, 4,
440 Offset(0x2B0), /* Port 3 Serial ATA error */
441 , 16,
442 P3PR, 1,
443 }
444 }
446 #include "acpi/routing.asl"
448 Scope(\_SB) {
449 Method(OSFL, 0){
450 if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
451 if(CondRefOf(\_OSI,Local1))
452 {
453 Store(1, OSVR) /* Assume some form of XP */
454 if (\_OSI("Windows 2006")) /* Vista */
455 {
456 Store(2, OSVR)
457 }
458 } else {
459 If(WCMP(\_OS,"Linux")) {
460 Store(3, OSVR) /* Linux */
461 } Else {
462 Store(4, OSVR) /* Gotta be WinCE */
463 }
464 }
465 Return(OSVR)
466 }
468 Method(_PIC, 0x01, NotSerialized)
469 {
470 If (Arg0)
471 {
472 \_SB.CIRQ()
473 }
474 Store(Arg0, PMOD)
475 }
476 Method(CIRQ, 0x00, NotSerialized){
477 Store(0, PINA)
478 Store(0, PINB)
479 Store(0, PINC)
480 Store(0, PIND)
481 Store(0, PINE)
482 Store(0, PINF)
483 Store(0, PING)
484 Store(0, PINH)
485 }
487 Name(IRQB, ResourceTemplate(){
488 IRQ(Level,ActiveLow,Shared){15}
489 })
491 Name(IRQP, ResourceTemplate(){
492 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
493 })
495 Name(PITF, ResourceTemplate(){
496 IRQ(Level,ActiveLow,Exclusive){9}
497 })
499 Device(INTA) {
500 Name(_HID, EISAID("PNP0C0F"))
501 Name(_UID, 1)
503 Method(_STA, 0) {
504 if (PINA) {
505 Return(0x0B) /* sata is invisible */
506 } else {
507 Return(0x09) /* sata is disabled */
508 }
509 } /* End Method(_SB.INTA._STA) */
511 Method(_DIS ,0) {
512 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
513 Store(0, PINA)
514 } /* End Method(_SB.INTA._DIS) */
516 Method(_PRS ,0) {
517 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
518 Return(IRQP)
519 } /* Method(_SB.INTA._PRS) */
521 Method(_CRS ,0) {
522 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
523 CreateWordField(IRQB, 0x1, IRQN)
524 ShiftLeft(1, PINA, IRQN)
525 Return(IRQB)
526 } /* Method(_SB.INTA._CRS) */
528 Method(_SRS, 1) {
529 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
530 CreateWordField(ARG0, 1, IRQM)
532 /* Use lowest available IRQ */
533 FindSetRightBit(IRQM, Local0)
534 if (Local0) {
535 Decrement(Local0)
536 }
537 Store(Local0, PINA)
538 } /* End Method(_SB.INTA._SRS) */
539 } /* End Device(INTA) */
541 Device(INTB) {
542 Name(_HID, EISAID("PNP0C0F"))
543 Name(_UID, 2)
545 Method(_STA, 0) {
546 if (PINB) {
547 Return(0x0B) /* sata is invisible */
548 } else {
549 Return(0x09) /* sata is disabled */
550 }
551 } /* End Method(_SB.INTB._STA) */
553 Method(_DIS ,0) {
554 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
555 Store(0, PINB)
556 } /* End Method(_SB.INTB._DIS) */
558 Method(_PRS ,0) {
559 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
560 Return(IRQP)
561 } /* Method(_SB.INTB._PRS) */
563 Method(_CRS ,0) {
564 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
565 CreateWordField(IRQB, 0x1, IRQN)
566 ShiftLeft(1, PINB, IRQN)
567 Return(IRQB)
568 } /* Method(_SB.INTB._CRS) */
570 Method(_SRS, 1) {
571 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
572 CreateWordField(ARG0, 1, IRQM)
574 /* Use lowest available IRQ */
575 FindSetRightBit(IRQM, Local0)
576 if (Local0) {
577 Decrement(Local0)
578 }
579 Store(Local0, PINB)
580 } /* End Method(_SB.INTB._SRS) */
581 } /* End Device(INTB) */
583 Device(INTC) {
584 Name(_HID, EISAID("PNP0C0F"))
585 Name(_UID, 3)
587 Method(_STA, 0) {
588 if (PINC) {
589 Return(0x0B) /* sata is invisible */
590 } else {
591 Return(0x09) /* sata is disabled */
592 }
593 } /* End Method(_SB.INTC._STA) */
595 Method(_DIS ,0) {
596 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
597 Store(0, PINC)
598 } /* End Method(_SB.INTC._DIS) */
600 Method(_PRS ,0) {
601 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
602 Return(IRQP)
603 } /* Method(_SB.INTC._PRS) */
605 Method(_CRS ,0) {
606 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
607 CreateWordField(IRQB, 0x1, IRQN)
608 ShiftLeft(1, PINC, IRQN)
609 Return(IRQB)
610 } /* Method(_SB.INTC._CRS) */
612 Method(_SRS, 1) {
613 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
614 CreateWordField(ARG0, 1, IRQM)
616 /* Use lowest available IRQ */
617 FindSetRightBit(IRQM, Local0)
618 if (Local0) {
619 Decrement(Local0)
620 }
621 Store(Local0, PINC)
622 } /* End Method(_SB.INTC._SRS) */
623 } /* End Device(INTC) */
625 Device(INTD) {
626 Name(_HID, EISAID("PNP0C0F"))
627 Name(_UID, 4)
629 Method(_STA, 0) {
630 if (PIND) {
631 Return(0x0B) /* sata is invisible */
632 } else {
633 Return(0x09) /* sata is disabled */
634 }
635 } /* End Method(_SB.INTD._STA) */
637 Method(_DIS ,0) {
638 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
639 Store(0, PIND)
640 } /* End Method(_SB.INTD._DIS) */
642 Method(_PRS ,0) {
643 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
644 Return(IRQP)
645 } /* Method(_SB.INTD._PRS) */
647 Method(_CRS ,0) {
648 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
649 CreateWordField(IRQB, 0x1, IRQN)
650 ShiftLeft(1, PIND, IRQN)
651 Return(IRQB)
652 } /* Method(_SB.INTD._CRS) */
654 Method(_SRS, 1) {
655 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
656 CreateWordField(ARG0, 1, IRQM)
658 /* Use lowest available IRQ */
659 FindSetRightBit(IRQM, Local0)
660 if (Local0) {
661 Decrement(Local0)
662 }
663 Store(Local0, PIND)
664 } /* End Method(_SB.INTD._SRS) */
665 } /* End Device(INTD) */
667 Device(INTE) {
668 Name(_HID, EISAID("PNP0C0F"))
669 Name(_UID, 5)
671 Method(_STA, 0) {
672 if (PINE) {
673 Return(0x0B) /* sata is invisible */
674 } else {
675 Return(0x09) /* sata is disabled */
676 }
677 } /* End Method(_SB.INTE._STA) */
679 Method(_DIS ,0) {
680 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
681 Store(0, PINE)
682 } /* End Method(_SB.INTE._DIS) */
684 Method(_PRS ,0) {
685 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
686 Return(IRQP)
687 } /* Method(_SB.INTE._PRS) */
689 Method(_CRS ,0) {
690 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
691 CreateWordField(IRQB, 0x1, IRQN)
692 ShiftLeft(1, PINE, IRQN)
693 Return(IRQB)
694 } /* Method(_SB.INTE._CRS) */
696 Method(_SRS, 1) {
697 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
698 CreateWordField(ARG0, 1, IRQM)
700 /* Use lowest available IRQ */
701 FindSetRightBit(IRQM, Local0)
702 if (Local0) {
703 Decrement(Local0)
704 }
705 Store(Local0, PINE)
706 } /* End Method(_SB.INTE._SRS) */
707 } /* End Device(INTE) */
709 Device(INTF) {
710 Name(_HID, EISAID("PNP0C0F"))
711 Name(_UID, 6)
713 Method(_STA, 0) {
714 if (PINF) {
715 Return(0x0B) /* sata is invisible */
716 } else {
717 Return(0x09) /* sata is disabled */
718 }
719 } /* End Method(_SB.INTF._STA) */
721 Method(_DIS ,0) {
722 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
723 Store(0, PINF)
724 } /* End Method(_SB.INTF._DIS) */
726 Method(_PRS ,0) {
727 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
728 Return(PITF)
729 } /* Method(_SB.INTF._PRS) */
731 Method(_CRS ,0) {
732 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
733 CreateWordField(IRQB, 0x1, IRQN)
734 ShiftLeft(1, PINF, IRQN)
735 Return(IRQB)
736 } /* Method(_SB.INTF._CRS) */
738 Method(_SRS, 1) {
739 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
740 CreateWordField(ARG0, 1, IRQM)
742 /* Use lowest available IRQ */
743 FindSetRightBit(IRQM, Local0)
744 if (Local0) {
745 Decrement(Local0)
746 }
747 Store(Local0, PINF)
748 } /* End Method(_SB.INTF._SRS) */
749 } /* End Device(INTF) */
751 Device(INTG) {
752 Name(_HID, EISAID("PNP0C0F"))
753 Name(_UID, 7)
755 Method(_STA, 0) {
756 if (PING) {
757 Return(0x0B) /* sata is invisible */
758 } else {
759 Return(0x09) /* sata is disabled */
760 }
761 } /* End Method(_SB.INTG._STA) */
763 Method(_DIS ,0) {
764 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
765 Store(0, PING)
766 } /* End Method(_SB.INTG._DIS) */
768 Method(_PRS ,0) {
769 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
770 Return(IRQP)
771 } /* Method(_SB.INTG._CRS) */
773 Method(_CRS ,0) {
774 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
775 CreateWordField(IRQB, 0x1, IRQN)
776 ShiftLeft(1, PING, IRQN)
777 Return(IRQB)
778 } /* Method(_SB.INTG._CRS) */
780 Method(_SRS, 1) {
781 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
782 CreateWordField(ARG0, 1, IRQM)
784 /* Use lowest available IRQ */
785 FindSetRightBit(IRQM, Local0)
786 if (Local0) {
787 Decrement(Local0)
788 }
789 Store(Local0, PING)
790 } /* End Method(_SB.INTG._SRS) */
791 } /* End Device(INTG) */
793 Device(INTH) {
794 Name(_HID, EISAID("PNP0C0F"))
795 Name(_UID, 8)
797 Method(_STA, 0) {
798 if (PINH) {
799 Return(0x0B) /* sata is invisible */
800 } else {
801 Return(0x09) /* sata is disabled */
802 }
803 } /* End Method(_SB.INTH._STA) */
805 Method(_DIS ,0) {
806 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
807 Store(0, PINH)
808 } /* End Method(_SB.INTH._DIS) */
810 Method(_PRS ,0) {
811 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
812 Return(IRQP)
813 } /* Method(_SB.INTH._CRS) */
815 Method(_CRS ,0) {
816 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
817 CreateWordField(IRQB, 0x1, IRQN)
818 ShiftLeft(1, PINH, IRQN)
819 Return(IRQB)
820 } /* Method(_SB.INTH._CRS) */
822 Method(_SRS, 1) {
823 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
824 CreateWordField(ARG0, 1, IRQM)
826 /* Use lowest available IRQ */
827 FindSetRightBit(IRQM, Local0)
828 if (Local0) {
829 Decrement(Local0)
830 }
831 Store(Local0, PINH)
832 } /* End Method(_SB.INTH._SRS) */
833 } /* End Device(INTH) */
835 } /* End Scope(_SB) */
838 /* Supported sleep states: */
839 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
841 If (LAnd(SSFG, 0x01)) {
842 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
843 }
844 If (LAnd(SSFG, 0x02)) {
845 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
846 }
847 If (LAnd(SSFG, 0x04)) {
848 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
849 }
850 If (LAnd(SSFG, 0x08)) {
851 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
852 }
854 Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
856 Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
857 Name(CSMS, 0) /* Current System State */
859 /* Wake status package */
860 Name(WKST,Package(){Zero, Zero})
862 /*
863 * \_PTS - Prepare to Sleep method
864 *
865 * Entry:
866 * Arg0=The value of the sleeping state S1=1, S2=2, etc
867 *
868 * Exit:
869 * -none-
870 *
871 * The _PTS control method is executed at the beginning of the sleep process
872 * for S1-S5. The sleeping value is passed to the _PTS control method. This
873 * control method may be executed a relatively long time before entering the
874 * sleep state and the OS may abort the operation without notification to
875 * the ACPI driver. This method cannot modify the configuration or power
876 * state of any device in the system.
877 */
878 Method(\_PTS, 1) {
879 /* DBGO("\\_PTS\n") */
880 /* DBGO("From S0 to S") */
881 /* DBGO(Arg0) */
882 /* DBGO("\n") */
884 /* Don't allow PCIRST# to reset USB */
885 if (LEqual(Arg0,3)){
886 Store(0,URRE)
887 }
889 /* Clear sleep SMI status flag and enable sleep SMI trap. */
890 /*Store(One, CSSM)
891 Store(One, SSEN)*/
893 /* On older chips, clear PciExpWakeDisEn */
894 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
895 * Store(0,\_SB.PWDE)
896 *}
897 */
899 /* Clear wake status structure. */
900 Store(0, Index(WKST,0))
901 Store(0, Index(WKST,1))
902 \_SB.PCI0.SIOS (Arg0)
903 } /* End Method(\_PTS) */
905 /*
906 * The following method results in a "not a valid reserved NameSeg"
907 * warning so I have commented it out for the duration. It isn't
908 * used, so it could be removed.
909 *
910 *
911 * \_GTS OEM Going To Sleep method
912 *
913 * Entry:
914 * Arg0=The value of the sleeping state S1=1, S2=2
915 *
916 * Exit:
917 * -none-
918 *
919 * Method(\_GTS, 1) {
920 * DBGO("\\_GTS\n")
921 * DBGO("From S0 to S")
922 * DBGO(Arg0)
923 * DBGO("\n")
924 * }
925 */
927 /*
928 * \_BFS OEM Back From Sleep method
929 *
930 * Entry:
931 * Arg0=The value of the sleeping state S1=1, S2=2
932 *
933 * Exit:
934 * -none-
935 */
936 Method(\_BFS, 1) {
937 /* DBGO("\\_BFS\n") */
938 /* DBGO("From S") */
939 /* DBGO(Arg0) */
940 /* DBGO(" to S0\n") */
941 }
943 /*
944 * \_WAK System Wake method
945 *
946 * Entry:
947 * Arg0=The value of the sleeping state S1=1, S2=2
948 *
949 * Exit:
950 * Return package of 2 DWords
951 * Dword 1 - Status
952 * 0x00000000 wake succeeded
953 * 0x00000001 Wake was signaled but failed due to lack of power
954 * 0x00000002 Wake was signaled but failed due to thermal condition
955 * Dword 2 - Power Supply state
956 * if non-zero the effective S-state the power supply entered
957 */
958 Method(\_WAK, 1) {
959 /* DBGO("\\_WAK\n") */
960 /* DBGO("From S") */
961 /* DBGO(Arg0) */
962 /* DBGO(" to S0\n") */
964 /* Re-enable HPET */
965 Store(1,HPDE)
967 /* Restore PCIRST# so it resets USB */
968 if (LEqual(Arg0,3)){
969 Store(1,URRE)
970 }
972 /* Arbitrarily clear PciExpWakeStatus */
973 Store(PWST, PWST)
975 /* if(DeRefOf(Index(WKST,0))) {
976 * Store(0, Index(WKST,1))
977 * } else {
978 * Store(Arg0, Index(WKST,1))
979 * }
980 */
981 \_SB.PCI0.SIOW (Arg0)
982 Return(WKST)
983 } /* End Method(\_WAK) */
985 Scope(\_GPE) { /* Start Scope GPE */
986 /* General event 0 */
987 Method(_L00) {
988 //DBGO("\\_GPE\\_L00\n")
989 }
991 /* General event 1 */
992 Method(_L01) {
993 //DBGO("\\_GPE\\_L01\n")
994 }
996 /* General event 2 */
997 Method(_L02) {
998 //DBGO("\\_GPE\\_L02\n")
999 }
1001 /* General event 3 */
1002 Method(_L03) {
1003 //DBGO("\\_GPE\\_L00\n")
1004 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1005 }
1007 /* General event 4 */
1008 Method(_L04) {
1009 //DBGO("\\_GPE\\_L04\n")
1010 }
1012 /* General event 5 */
1013 Method(_L05) {
1014 //DBGO("\\_GPE\\_L05\n")
1015 }
1017 /* _L06 General event 6 - Used for GPM6, moved to USB.asl */
1018 /* _L07 General event 7 - Used for GPM7, moved to USB.asl */
1020 /* Legacy PM event */
1021 Method(_L08) {
1022 //DBGO("\\_GPE\\_L08\n")
1023 }
1025 /* Temp warning (TWarn) event */
1026 Method(_L09) {
1027 //DBGO("\\_GPE\\_L09\n")
1028 Notify (\_TZ.TZ00, 0x80)
1029 }
1031 /* Reserved */
1032 Method(_L0A) {
1033 //DBGO("\\_GPE\\_L0A\n")
1034 }
1036 /* USB controller PME# */
1037 Method(_L0B) {
1038 //DBGO("\\_GPE\\_L0B\n")
1039 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1040 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1041 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1042 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1043 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1044 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1045 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1046 }
1048 /* AC97 controller PME# */
1049 Method(_L0C) {
1050 //DBGO("\\_GPE\\_L0C\n")
1051 }
1053 /* OtherTherm PME# */
1054 Method(_L0D) {
1055 //DBGO("\\_GPE\\_L0D\n")
1056 }
1058 /* _L0E GPM9 SCI event - Moved to USB.asl */
1060 /* PCIe HotPlug event */
1061 Method(_L0F) {
1062 //DBGO("\\_GPE\\_L0F\n")
1063 }
1065 /* ExtEvent0 SCI event */
1066 Method(_L10) {
1067 //DBGO("\\_GPE\\_L10\n")
1068 }
1071 /* ExtEvent1 SCI event */
1072 Method(_L11) {
1073 //DBGO("\\_GPE\\_L11\n")
1074 }
1076 /* PCIe PME# event */
1077 Method(_L12) {
1078 //DBGO("\\_GPE\\_L12\n")
1079 }
1081 /* _L13 GPM0 SCI event - Moved to USB.asl */
1082 /* _L14 GPM1 SCI event - Moved to USB.asl */
1083 /* _L15 GPM2 SCI event - Moved to USB.asl */
1084 /* _L16 GPM3 SCI event - Moved to USB.asl */
1085 /* _L17 GPM8 SCI event - Moved to USB.asl */
1087 /* GPIO0 or GEvent8 event */
1088 Method(_L18) {
1089 //DBGO("\\_GPE\\_L18\n")
1090 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1091 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1092 Notify(\_SB.PCI0.PBRb, 0x02) /* NOTIFY_DEVICE_WAKE */
1093 Notify(\_SB.PCI0.PBRc, 0x02) /* NOTIFY_DEVICE_WAKE */
1094 Notify(\_SB.PCI0.PBRd, 0x02) /* NOTIFY_DEVICE_WAKE */
1095 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1096 }
1098 /* _L19 GPM4 SCI event - Moved to USB.asl */
1099 /* _L1A GPM5 SCI event - Moved to USB.asl */
1101 /* Azalia SCI event */
1102 Method(_L1B) {
1103 //DBGO("\\_GPE\\_L1B\n")
1104 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1105 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1106 }
1108 /* GPM6 SCI event - Reassigned to _L06 */
1109 Method(_L1C) {
1110 //DBGO("\\_GPE\\_L1C\n")
1111 }
1113 /* GPM7 SCI event - Reassigned to _L07 */
1114 Method(_L1D) {
1115 //DBGO("\\_GPE\\_L1D\n")
1116 }
1118 /* GPIO2 or GPIO66 SCI event */
1119 Method(_L1E) {
1120 //DBGO("\\_GPE\\_L1E\n")
1121 }
1123 /* _L1F SATA SCI event - Moved to sata.asl */
1125 } /* End Scope GPE */
1127 #include "acpi/usb.asl"
1129 /* System Bus */
1130 Scope(\_SB) { /* Start \_SB scope */
1131 #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
1133 /* _SB.PCI0 */
1134 /* Note: Only need HID on Primary Bus */
1135 Device(PCI0) {
1136 External (TOM1) //assigned when update_ssdt()
1137 External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
1139 Name(_HID, EISAID("PNP0A03"))
1140 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1141 Method(_BBN, 0) { /* Bus number = 0 */
1142 Return(0)
1143 }
1144 Method(_STA, 0) {
1145 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1146 Return(0x0B) /* Status is visible */
1147 }
1149 Method(_PRT,0) {
1150 If(PMOD){ Return(APR0) } /* APIC mode */
1151 Return (PR0) /* PIC Mode */
1152 } /* end _PRT */
1154 /* Describe the Northbridge devices */
1155 Device(AMRT) {
1156 Name(_ADR, 0x00000000)
1157 } /* end AMRT */
1159 /* The external GFX bridge */
1160 Device(PBR2) {
1161 Name(_ADR, 0x00020000)
1162 Name(_PRW, Package() {0x18, 4})
1163 Method(_PRT,0) {
1164 If(PMOD){ Return(APS2) } /* APIC mode */
1165 Return (PS2) /* PIC Mode */
1166 } /* end _PRT */
1167 } /* end PBR2 */
1169 /* Dev3 is also an external GFX bridge */
1171 Device(PBR4) {
1172 Name(_ADR, 0x00040000)
1173 Name(_PRW, Package() {0x18, 4})
1174 Method(_PRT,0) {
1175 If(PMOD){ Return(APS4) } /* APIC mode */
1176 Return (PS4) /* PIC Mode */
1177 } /* end _PRT */
1178 } /* end PBR4 */
1180 Device(PBRb) {
1181 Name(_ADR, 0x000b0000)
1182 Name(_PRW, Package() {0x18, 4})
1183 Method(_PRT,0) {
1184 If(PMOD){ Return(APSb) } /* APIC mode */
1185 Return (PSb) /* PIC Mode */
1186 } /* end _PRT */
1187 } /* end PBRb */
1189 Device(PBRc) {
1190 Name(_ADR, 0x000c0000)
1191 Name(_PRW, Package() {0x18, 4})
1192 Method(_PRT,0) {
1193 If(PMOD){ Return(APSc) } /* APIC mode */
1194 Return (PSc) /* PIC Mode */
1195 } /* end _PRT */
1196 } /* end PBRc */
1198 Device(PBRd) {
1199 Name(_ADR, 0x000d0000)
1200 Name(_PRW, Package() {0x18, 4})
1201 Method(_PRT,0) {
1202 If(PMOD){ Return(APSd) } /* APIC mode */
1203 Return (PSd) /* PIC Mode */
1204 } /* end _PRT */
1205 } /* end PBRd */
1207 /* PCI slot 1, 2, 3 */
1208 Device(PIBR) {
1209 Name(_ADR, 0x00140004)
1210 Name(_PRW, Package() {0x18, 4})
1212 Method(_PRT, 0) {
1213 Return (PCIB)
1214 }
1215 }
1217 /* Describe the Southbridge devices */
1218 Device(STCR) {
1219 Name(_ADR, 0x00110000)
1220 #include "acpi/sata.asl"
1221 } /* end STCR */
1223 Device(UOH1) {
1224 Name(_ADR, 0x00130000)
1225 Name(_PRW, Package() {0x0B, 3})
1226 } /* end UOH1 */
1228 Device(UOH2) {
1229 Name(_ADR, 0x00130001)
1230 Name(_PRW, Package() {0x0B, 3})
1231 } /* end UOH2 */
1233 Device(UOH3) {
1234 Name(_ADR, 0x00130002)
1235 Name(_PRW, Package() {0x0B, 3})
1236 } /* end UOH3 */
1238 Device(UOH4) {
1239 Name(_ADR, 0x00130003)
1240 Name(_PRW, Package() {0x0B, 3})
1241 } /* end UOH4 */
1243 Device(UOH5) {
1244 Name(_ADR, 0x00130004)
1245 Name(_PRW, Package() {0x0B, 3})
1246 } /* end UOH5 */
1248 Device(UEH1) {
1249 Name(_ADR, 0x00130005)
1250 Name(_PRW, Package() {0x0B, 3})
1251 } /* end UEH1 */
1253 Device(SBUS) {
1254 Name(_ADR, 0x00140000)
1255 } /* end SBUS */
1257 /* Primary (and only) IDE channel */
1258 Device(IDEC) {
1259 Name(_ADR, 0x00140001)
1260 #include "acpi/ide.asl"
1261 } /* end IDEC */
1263 Device(AZHD) {
1264 Name(_ADR, 0x00140002)
1265 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1266 Field(AZPD, AnyAcc, NoLock, Preserve) {
1267 offset (0x42),
1268 NSDI, 1,
1269 NSDO, 1,
1270 NSEN, 1,
1271 offset (0x44),
1272 IPCR, 4,
1273 offset (0x54),
1274 PWST, 2,
1275 , 6,
1276 PMEB, 1,
1277 , 6,
1278 PMST, 1,
1279 offset (0x62),
1280 MMCR, 1,
1281 offset (0x64),
1282 MMLA, 32,
1283 offset (0x68),
1284 MMHA, 32,
1285 offset (0x6C),
1286 MMDT, 16,
1287 }
1289 Method(_INI) {
1290 If(LEqual(OSVR,3)){ /* If we are running Linux */
1291 Store(zero, NSEN)
1292 Store(one, NSDO)
1293 Store(one, NSDI)
1294 }
1295 }
1296 } /* end AZHD */
1298 Device(LIBR) {
1299 Name(_ADR, 0x00140003)
1300 /* Method(_INI) {
1301 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1302 } */ /* End Method(_SB.SBRDG._INI) */
1304 /* Real Time Clock Device */
1305 Device(RTC0) {
1306 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
1307 Name(_CRS, ResourceTemplate() {
1308 IRQNoFlags(){8}
1309 IO(Decode16,0x0070, 0x0070, 0, 2)
1310 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1311 })
1312 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1314 Device(TMR) { /* Timer */
1315 Name(_HID,EISAID("PNP0100")) /* System Timer */
1316 Name(_CRS, ResourceTemplate() {
1317 IRQNoFlags(){0}
1318 IO(Decode16, 0x0040, 0x0040, 0, 4)
1319 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1320 })
1321 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1323 Device(SPKR) { /* Speaker */
1324 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1325 Name(_CRS, ResourceTemplate() {
1326 IO(Decode16, 0x0061, 0x0061, 0, 1)
1327 })
1328 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1330 Device(PIC) {
1331 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1332 Name(_CRS, ResourceTemplate() {
1333 IRQNoFlags(){2}
1334 IO(Decode16,0x0020, 0x0020, 0, 2)
1335 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1336 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1337 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1338 })
1339 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1341 Device(MAD) { /* 8257 DMA */
1342 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1343 Name(_CRS, ResourceTemplate() {
1344 DMA(Compatibility,BusMaster,Transfer8){4}
1345 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1346 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1347 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1348 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1349 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1350 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1351 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1352 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1354 Device(COPR) {
1355 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1356 Name(_CRS, ResourceTemplate() {
1357 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1358 IRQNoFlags(){13}
1359 })
1360 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1362 Device (PS2M) {
1363 Name (_HID, EisaId ("PNP0F13"))
1364 Name (_CRS, ResourceTemplate () {
1365 IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
1366 IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
1367 IRQNoFlags () {12}
1368 })
1369 Method (_STA, 0, NotSerialized) {
1370 And (FLG0, 0x04, Local0)
1371 If (LEqual (Local0, 0x04)) {
1372 Return (0x0F)
1373 } Else {
1374 Return (0x00)
1375 }
1376 }
1377 }
1379 Device (PS2K) {
1380 Name (_HID, EisaId ("PNP0303"))
1381 Method (_STA, 0, NotSerialized) {
1382 And (FLG0, 0x04, Local0)
1383 If (LEqual (Local0, 0x04)) {
1384 Return (0x0F)
1385 } Else {
1386 Return (0x00)
1387 }
1388 }
1389 Name (_CRS, ResourceTemplate () {
1390 IO (Decode16, 0x0060, 0x0060, 0x00, 0x01)
1391 IO (Decode16, 0x0064, 0x0064, 0x00, 0x01)
1392 IRQNoFlags () {1}
1393 })
1394 }
1396 #if 0 //acpi_create_hpet
1397 Device(HPET) {
1398 Name(_HID,EISAID("PNP0103"))
1399 Name(CRS, ResourceTemplate() {
1400 IRQNoFlags () {0}
1401 IRQNoFlags () {2}
1402 IRQNoFlags () {8}
1403 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, MNT) /* 1kb reserved space */
1404 })
1405 Method(_STA, 0, NotSerialized) {
1406 Return(0x0F) /* sata is visible */
1407 }
1408 Method(_CRS, 0, NotSerialized) {
1409 CreateDwordField(CRS, ^MNT._BAS, HPT)
1410 Store(HPBA, HPT)
1411 Return(CRS)
1412 }
1413 } /* End Device(_SB.PCI0.LIBR.HPET) */
1414 #endif
1415 } /* end LIBR */
1417 Device(HPBR) {
1418 Name(_ADR, 0x00140004)
1419 } /* end HostPciBr */
1421 Device(ACAD) {
1422 Name(_ADR, 0x00140005)
1423 } /* end Ac97audio */
1425 Device(ACMD) {
1426 Name(_ADR, 0x00140006)
1427 } /* end Ac97modem */
1429 /* ITE8718 Support */
1430 OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
1431 Field (IOID, ByteAcc, NoLock, Preserve)
1432 {
1433 SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
1434 }
1436 IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
1437 {
1438 Offset (0x07),
1439 LDN, 8, /* Logical Device Number */
1440 Offset (0x20),
1441 CID1, 8, /* Chip ID Byte 1, 0x87 */
1442 CID2, 8, /* Chip ID Byte 2, 0x12 */
1443 Offset (0x30),
1444 ACTR, 8, /* Function activate */
1445 Offset (0xF0),
1446 APC0, 8, /* APC/PME Event Enable Register */
1447 APC1, 8, /* APC/PME Status Register */
1448 APC2, 8, /* APC/PME Control Register 1 */
1449 APC3, 8, /* Environment Controller Special Configuration Register */
1450 APC4, 8 /* APC/PME Control Register 2 */
1451 }
1453 /* Enter the 8718 MB PnP Mode */
1454 Method (EPNP)
1455 {
1456 Store(0x87, SIOI)
1457 Store(0x01, SIOI)
1458 Store(0x55, SIOI)
1459 Store(0x55, SIOI) /* 8718 magic number */
1460 }
1461 /* Exit the 8718 MB PnP Mode */
1462 Method (XPNP)
1463 {
1464 Store (0x02, SIOI)
1465 Store (0x02, SIOD)
1466 }
1467 /*
1468 * Keyboard PME is routed to SB700 Gevent3. We can wake
1469 * up the system by pressing the key.
1470 */
1471 Method (SIOS, 1)
1472 {
1473 /* We only enable KBD PME for S5. */
1474 If (LLess (Arg0, 0x05))
1475 {
1476 EPNP()
1477 /* DBGO("8718F\n") */
1479 Store (0x4, LDN)
1480 Store (One, ACTR) /* Enable EC */
1481 /*
1482 Store (0x4, LDN)
1483 Store (0x04, APC4)
1484 */ /* falling edge. which mode? Not sure. */
1486 Store (0x4, LDN)
1487 Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
1488 Store (0x4, LDN)
1489 Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
1491 XPNP()
1492 }
1493 }
1494 Method (SIOW, 1)
1495 {
1496 EPNP()
1497 Store (0x4, LDN)
1498 Store (Zero, APC0) /* disable keyboard PME */
1499 Store (0x4, LDN)
1500 Store (0xFF, APC1) /* clear keyboard PME status */
1501 XPNP()
1502 }
1504 Name (CRS, ResourceTemplate ()
1505 {
1506 WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
1507 0x0000, // Granularity
1508 0x0000, // Range Minimum
1509 0x00FF, // Range Maximum
1510 0x0000, // Translation Offset
1511 0x0100, // Length
1512 ,,)
1513 IO (Decode16,
1514 0x0CF8, // Range Minimum
1515 0x0CF8, // Range Maximum
1516 0x01, // Alignment
1517 0x08, // Length
1518 )
1520 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1521 0x0000, // Granularity
1522 0x0000, // Range Minimum
1523 0x03AF, // Range Maximum
1524 0x0000, // Translation Offset
1525 0x03B0, // Length
1526 ,, , TypeStatic)
1527 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1528 0x0000, // Granularity
1529 0x03E0, // Range Minimum
1530 0x0CF7, // Range Maximum
1531 0x0000, // Translation Offset
1532 0x0918, // Length
1533 ,, , TypeStatic)
1535 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1536 0x0000, // Granularity
1537 0x03B0, // Range Minimum
1538 0x03BB, // Range Maximum
1539 0x0000, // Translation Offset
1540 0x000C, // Length
1541 ,, , TypeStatic)
1542 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1543 0x0000, // Granularity
1544 0x03C0, // Range Minimum
1545 0x03DF, // Range Maximum
1546 0x0000, // Translation Offset
1547 0x0020, // Length
1548 ,, , TypeStatic)
1549 WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1550 0x0000, // Granularity
1551 0x0D00, // Range Minimum
1552 0xFFFF, // Range Maximum
1553 0x0000, // Translation Offset
1554 0xF300, // Length
1555 ,, , TypeStatic)
1556 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) // VGA memory space
1558 Memory32Fixed (ReadOnly,
1559 0xE0000000, // Address Base
1560 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default)
1561 MMIO)
1562 })
1564 Method (_CRS, 0, NotSerialized)
1565 {
1566 CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1)
1567 CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1)
1569 /*
1570 * Declare memory between TOM1 and 4GB as available
1571 * for PCI MMIO.
1572 * Use ShiftLeft to avoid 64bit constant (for XP).
1573 * This will work even if the OS does 32bit arithmetic, as
1574 * 32bit (0x00000000 - TOM1) will wrap and give the same
1575 * result as 64bit (0x100000000 - TOM1).
1576 */
1577 Store(TOM1, BAS1)
1578 ShiftLeft(0x10000000, 4, Local0)
1579 Subtract(Local0, TOM1, Local0)
1580 Store(Local0, LEN1)
1581 //DBGO(TOM1)
1583 Return (CRS)
1584 }
1586 /*
1587 *
1588 * FIRST METHOD CALLED UPON BOOT
1589 *
1590 * 1. If debugging, print current OS and ACPI interpreter.
1591 * 2. Get PCI Interrupt routing from ACPI VSM, this
1592 * value is based on user choice in BIOS setup.
1593 */
1594 Method(_INI, 0) {
1595 /* DBGO("\\_SB\\_INI\n") */
1596 /* DBGO(" DSDT.ASL code from ") */
1597 /* DBGO(__DATE__) */
1598 /* DBGO(" ") */
1599 /* DBGO(__TIME__) */
1600 /* DBGO("\n Sleep states supported: ") */
1601 /* DBGO("\n") */
1602 /* DBGO(" \\_OS=") */
1603 /* DBGO(\_OS) */
1604 /* DBGO("\n \\_REV=") */
1605 /* DBGO(\_REV) */
1606 /* DBGO("\n") */
1608 /* Determine the OS we're running on */
1609 OSFL()
1610 /* On older chips, clear PciExpWakeDisEn */
1611 /*if (LLessEqual(\SBRI, 0x13)) {
1612 * Store(0,\PWDE)
1613 *}
1614 */
1615 } /* End Method(_SB._INI) */
1616 } /* End Device(PCI0) */
1618 Device(PWRB) { /* Start Power button device */
1619 Name(_HID, EISAID("PNP0C0C"))
1620 Name(_UID, 0xAA)
1621 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1622 Name(_STA, 0x0B) /* sata is invisible */
1623 }
1624 } /* End \_SB scope */
1626 Scope(\_SI) {
1627 Method(_SST, 1) {
1628 /* DBGO("\\_SI\\_SST\n") */
1629 /* DBGO(" New Indicator state: ") */
1630 /* DBGO(Arg0) */
1631 /* DBGO("\n") */
1632 }
1633 } /* End Scope SI */
1635 #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
1637 /* THERMAL */
1638 Scope(\_TZ) {
1639 Name (KELV, 2732)
1640 Name (THOT, 800)
1641 Name (TCRT, 850)
1643 ThermalZone(TZ00) {
1644 Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
1645 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1646 Return(Add(0, 2730))
1647 }
1648 Method(_AL0,0) { /* Returns package of cooling device to turn on */
1649 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1650 Return(Package() {\_TZ.TZ00.FAN0})
1651 }
1652 Device (FAN0) {
1653 Name(_HID, EISAID("PNP0C0B"))
1654 Name(_PR0, Package() {PFN0})
1655 }
1657 PowerResource(PFN0,0,0) {
1658 Method(_STA) {
1659 Store(0xF,Local0)
1660 Return(Local0)
1661 }
1662 Method(_ON) {
1663 /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1664 }
1665 Method(_OFF) {
1666 /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1667 }
1668 }
1670 Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
1671 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1672 Return (Add (THOT, KELV))
1673 }
1674 Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
1675 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1676 Return (Add (TCRT, KELV))
1677 }
1678 Method(_TMP,0) { /* return current temp of this zone */
1679 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1680 If (LGreater (Local0, 0x10)) {
1681 Store (Local0, Local1)
1682 }
1683 Else {
1684 Add (Local0, THOT, Local0)
1685 Return (Add (400, KELV))
1686 }
1688 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1689 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1690 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1691 If (LGreater (Local0, 0x10)) {
1692 If (LGreater (Local0, Local1)) {
1693 Store (Local0, Local1)
1694 }
1696 Multiply (Local1, 10, Local1)
1697 Return (Add (Local1, KELV))
1698 }
1699 Else {
1700 Add (Local0, THOT, Local0)
1701 Return (Add (400 , KELV))
1702 }
1703 } /* end of _TMP */
1704 } /* end of TZ00 */
1705 }
1706 }
1707 /* End of ASL file */