2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
20 #include "routing.asl"
24 /* Routing is in System Bus scope */
28 /* Bus 0, Dev 0 - SR5650 HT */
29 Package() { 0xFFFF, Zero, INTA, Zero },
31 /* Bus 0, Dev 1 - CLKCONFIG */
33 /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
34 Package() {0x0002FFFF, 0, INTE, 0 },
36 /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
37 Package() {0x0003FFFF, 0, INTE, 0 },
39 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
40 Package() {0x0004FFFF, 0, INTE, 0 },
42 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
43 Package() {0x0005FFFF, 0, INTE, 0 },
45 /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
46 Package() {0x0006FFFF, 0, INTF, 0 },
48 /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
49 Package() {0x0007FFFF, 0, INTF, 0 },
51 /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
53 /* Bus 0, Dev 9 - PCIe Bridge */
54 Package() {0x0009FFFF, 0, INTF, 0 },
56 /* Bus 0, Dev a - PCIe Bridge */
57 Package() {0x000AFFFF, 0, INTG, 0 },
59 /* Bus 0, Dev b - PCIe Bridge */
60 Package() {0x000BFFFF, 0, INTG, 0 },
62 /* Bus 0, Dev c - PCIe Bridge */
63 Package() {0x000CFFFF, 0, INTG, 0 },
65 /* Bus 0, Dev d - PCIe Bridge for Intel 82576 Giga NIC*/
68 /* Bus 0, Dev 17 - SATA controller */
69 Package() {0x0011FFFF, 0, INTG, 0 },
71 /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
72 * EHCI, dev 18, 19 func 2 */
73 Package() {0x0012FFFF, 0, INTA, 0 },
74 Package() {0x0012FFFF, 1, INTB, 0 },
75 Package() {0x0012FFFF, 2, INTC, 0 },
76 Package() {0x0012FFFF, 3, INTD, 0 },
78 Package() {0x0013FFFF, 0, INTC, 0 },
79 Package() {0x0013FFFF, 1, INTD, 0 },
80 Package() {0x0013FFFF, 2, INTA, 0 },
81 Package() {0x0013FFFF, 2, INTB, 0 },
83 /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
84 Package(){0x0014FFFF, 0, INTA, 0 },
85 Package(){0x0014FFFF, 1, INTB, 0 },
86 Package(){0x0014FFFF, 2, INTC, 0 },
87 Package(){0x0014FFFF, 3, INTD, 0 },
91 /* NB devices in APIC mode */
92 /* Bus 0, Dev 0 - SR5650 HT */
93 Package() { 0xFFFF, Zero, Zero, 0x37 },
95 /* Bus 0, Dev 1 - CLKCONFIG */
97 /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot (GFX0) */
98 Package() {0x0002FFFF, 0, 0, 0x34 },
100 /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
101 Package() {0x0003FFFF, 0, 0, 0x34 },
103 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
104 Package() {0x0004FFFF, 0, 0, 0x34 },
106 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
107 Package() {0x0005FFFF, 0, 0, 0x34 },
109 /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
110 Package() {0x0006FFFF, 0, 0, 0x35 },
112 /* Bus 0, Dev 7 - PCIe Bridge */
113 Package() {0x0007FFFF, 0, 0, 0x35 },
115 /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
117 /* Bus 0, Dev 9 - PCIe Bridge */
118 Package() {0x0009FFFF, 0, 0, 0x35 },
120 /* Bus 0, Dev A - PCIe Bridge */
121 Package() {0x000AFFFF, 0, 0, 0x36 },
123 /* Bus 0, Dev B - PCIe Bridge */
124 Package() {0x000BFFFF, 0, 0, 0x36 },
126 /* Bus 0, Dev C - PCIe Bridge */
127 Package() {0x000CFFFF, 0, 0, 0x36 },
129 /* Bus 0, Dev D - PCIe Bridge For Intel 82576 Giga NIC*/
131 /* SB devices in APIC mode */
132 /* Bus 0, Dev 17 - SATA controller */
133 Package() {0x0011FFFF, 0, 0, 0x16 },
135 /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
136 * EHCI, dev 18, 19 func 2 */
137 Package( ){0x0012FFFF, 0, 0, 16 },
138 Package() {0x0012FFFF, 1, 0, 17 },
139 Package() {0x0012FFFF, 2, 0, 18 },
140 Package() {0x0012FFFF, 3, 0, 19 },
142 Package() {0x0013FFFF, 0, 0, 18 },
143 Package() {0x0013FFFF, 1, 0, 19 },
144 Package() {0x0013FFFF, 2, 0, 16 },
145 Package() {0x0013FFFF, 3, 0, 17 },
147 /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
148 Package() {0x0014FFFF, 0, 0, 16 },
149 Package() {0x0014FFFF, 1, 0, 17 },
150 Package() {0x0014FFFF, 2, 0, 18 },
151 Package() {0x0014FFFF, 3, 0, 19 },
155 /* The external GFX - Hooked to PCIe slot 4 */
156 Package() {0x0000FFFF, 0, INTC, 0 },
157 Package() {0x0000FFFF, 1, INTD, 0 },
158 Package() {0x0000FFFF, 2, INTA, 0 },
159 Package() {0x0000FFFF, 3, INTB, 0 },
161 Name(APS2, Package(){
162 /* The external GFX - Hooked to PCIe slot 4 */
163 Package(){0x0000FFFF, 0, 0, 0x18 },
164 Package(){0x0000FFFF, 1, 0, 0x19 },
165 Package(){0x0000FFFF, 2, 0, 0x1A },
166 Package(){0x0000FFFF, 3, 0, 0x1B },
170 /* PCIe slot - Hooked to PCIe slot 4 */
171 Package(){0x0000FFFF, 0, INTA, 0 },
172 Package(){0x0000FFFF, 1, INTB, 0 },
173 Package(){0x0000FFFF, 2, INTC, 0 },
174 Package(){0x0000FFFF, 3, INTD, 0 },
176 Name(APS4, Package(){
177 /* PCIe slot - Hooked to PCIe slot 4 */
178 Package(){0x0000FFFF, 0, 0, 0x2C },
179 Package(){0x0000FFFF, 1, 0, 0x2D },
180 Package(){0x0000FFFF, 2, 0, 0x2E },
181 Package(){0x0000FFFF, 3, 0, 0x2F },
185 /* PCIe slot - Hooked to PCIe slot 11 */
186 Package(){0x0000FFFF, 0, INTD, 0 },
187 Package(){0x0000FFFF, 1, INTA, 0 },
188 Package(){0x0000FFFF, 2, INTB, 0 },
189 Package(){0x0000FFFF, 3, INTC, 0 },
191 Name(APSb, Package(){
192 /* PCIe slot - Hooked to PCIe */
193 Package(){0x0000FFFF, 0, 0, 0x20 },
194 Package(){0x0000FFFF, 1, 0, 0x21 },
195 Package(){0x0000FFFF, 2, 0, 0x22 },
196 Package(){0x0000FFFF, 3, 0, 0x23 },
200 /* PCIe slot - Hooked to PCIe slot 12 */
201 Package(){0x0000FFFF, 0, INTA, 0 },
202 Package(){0x0000FFFF, 1, INTB, 0 },
203 Package(){0x0000FFFF, 2, INTC, 0 },
204 Package(){0x0000FFFF, 3, INTD, 0 },
206 Name(APSc, Package(){
207 /* PCIe slot - Hooked to PCIe */
208 Package(){0x0000FFFF, 0, 0, 0x24 },
209 Package(){0x0000FFFF, 1, 0, 0x25 },
210 Package(){0x0000FFFF, 2, 0, 0x26 },
211 Package(){0x0000FFFF, 3, 0, 0x27 },
215 /* PCIe slot - Hooked to PCIe slot 13 */
216 Package(){0x0000FFFF, 0, INTB, 0 },
217 Package(){0x0000FFFF, 1, INTC, 0 },
218 Package(){0x0000FFFF, 2, INTD, 0 },
219 Package(){0x0000FFFF, 3, INTA, 0 },
222 Name(APSd, Package(){
223 /* PCIe slot - Hooked to PCIe */
224 Package(){0x0000FFFF, 0, 0, 0x28 },
225 Package(){0x0000FFFF, 1, 0, 0x29 },
226 Package(){0x0000FFFF, 2, 0, 0x2A },
227 Package(){0x0000FFFF, 3, 0, 0x2B },
230 Name(PCIB, Package(){
231 /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
232 Package(){0x0004FFFF, 0, 0, 0x14 },
233 Package(){0x0003FFFF, 0, 0, 0x15 },
234 Package(){0x0003FFFF, 1, 0, 0x16 },
235 Package(){0x0003FFFF, 2, 0, 0x17 },
236 Package(){0x0003FFFF, 3, 0, 0x14 },