src/mainboard/samsung/lumpy/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2010 coresystems GmbH
   5  * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <stdint.h>
  18 #include <string.h>
  19 #include <lib.h>
  20 #include <timestamp.h>
  21 #include <arch/io.h>
  22 #include <device/pci_def.h>
  23 #include <device/pnp_def.h>
  24 #include <cpu/x86/lapic.h>
  25 #include <pc80/mc146818rtc.h>
  26 #include <cbfs.h>
  27 #include <arch/acpi.h>
  28 #include <cbmem.h>
  29 #include <console/console.h>
  30 #include <bootmode.h>
  31 #include <tpm.h>
  32 #include <northbridge/intel/sandybridge/sandybridge.h>
  33 #include <northbridge/intel/sandybridge/raminit.h>
  34 #include <southbridge/intel/bd82x6x/pch.h>
  35 #include <southbridge/intel/bd82x6x/gpio.h>
  36 #include <arch/cpu.h>
  37 #include <cpu/x86/bist.h>
  38 #include <cpu/x86/msr.h>
  39 #include <halt.h>
  40 #include "option_table.h"
  41 #include "gpio.h"
  42 #if CONFIG_DRIVERS_UART_8250IO
  43 #include <superio/smsc/lpc47n207/lpc47n207.h>
  44 #endif
  45
  46 static void pch_enable_lpc(void)
  47 {
  48         /* Set COM1/COM2 decode range */
  49         pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
  50
  51 #if CONFIG_DRIVERS_UART_8250IO
  52         /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/
  53         pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
  54                 KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
  55
  56         /* map full 256 bytes at 0x1600 to the LPC bus */
  57         pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601);
  58
  59         try_enabling_LPC47N207_uart();
  60 #else
  61         /* Enable SuperIO + EC + KBC */
  62         pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
  63                 KBC_LPC_EN);
  64 #endif
  65 }
  66
  67 static void rcba_config(void)
  68 {
  69         u32 reg32;
  70
  71         /*
  72          *             GFX    INTA -> PIRQA (MSI)
  73          * D28IP_P1IP  WLAN   INTA -> PIRQB
  74          * D28IP_P4IP  ETH0   INTB -> PIRQC (MSI)
  75          * D29IP_E1P   EHCI1  INTA -> PIRQD
  76          * D26IP_E2P   EHCI2  INTA -> PIRQB
  77          * D31IP_SIP   SATA   INTA -> PIRQA (MSI)
  78          * D31IP_SMIP  SMBUS  INTC -> PIRQH
  79          * D31IP_TTIP  THRT   INTB -> PIRQG
  80          * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
  81          *
  82          * LIGHTSENSOR             -> PIRQE (Edge Triggered)
  83          * TRACKPAD                -> PIRQF (Edge Triggered)
  84          */
  85
  86         /* Device interrupt pin register (board specific) */
  87         RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
  88                 (INTC << D31IP_SMIP) | (INTA << D31IP_SIP);
  89         RCBA32(D30IP) = (NOINT << D30IP_PIP);
  90         RCBA32(D29IP) = (INTA << D29IP_E1P);
  91         RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
  92                 (INTB << D28IP_P4IP);
  93         RCBA32(D27IP) = (INTA << D27IP_ZIP);
  94         RCBA32(D26IP) = (INTA << D26IP_E2P);
  95         RCBA32(D25IP) = (NOINT << D25IP_LIP);
  96         RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
  97
  98         /* Device interrupt route registers */
  99         DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB);
 100         DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH);
 101         DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
 102         DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
 103         DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA);
 104         DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
 105         DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
 106
 107         /* Enable IOAPIC (generic) */
 108         RCBA16(OIC) = 0x0100;
 109         /* PCH BWG says to read back the IOAPIC enable register */
 110         (void) RCBA16(OIC);
 111
 112         /* Disable unused devices (board specific) */
 113         reg32 = RCBA32(FD);
 114         reg32 |= PCH_DISABLE_ALWAYS;
 115         RCBA32(FD) = reg32;
 116 }
 117
 118 static void early_pch_init(void)
 119 {
 120         u8 reg8;
 121
 122         // reset rtc power status
 123         reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4);
 124         reg8 &= ~(1 << 2);
 125         pci_write_config8(PCH_LPC_DEV, 0xa4, reg8);
 126 }
 127
 128 #include <cpu/intel/romstage.h>
 129 void main(unsigned long bist)
 130 {
 131         int boot_mode = 0;
 132         int cbmem_was_initted;
 133
 134         struct pei_data pei_data = {
 135                 .pei_version = PEI_VERSION,
 136                 .mchbar = (uintptr_t)DEFAULT_MCHBAR,
 137                 .dmibar = (uintptr_t)DEFAULT_DMIBAR,
 138                 .epbar = DEFAULT_EPBAR,
 139                 .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
 140                 .smbusbar = SMBUS_IO_BASE,
 141                 .wdbbar = 0x4000000,
 142                 .wdbsize = 0x1000,
 143                 .hpet_address = CONFIG_HPET_ADDRESS,
 144                 .rcba = (uintptr_t)DEFAULT_RCBABASE,
 145                 .pmbase = DEFAULT_PMBASE,
 146                 .gpiobase = DEFAULT_GPIOBASE,
 147                 .thermalbase = 0xfed08000,
 148                 .system_type = 0, // 0 Mobile, 1 Desktop/Server
 149                 .tseg_size = CONFIG_SMM_TSEG_SIZE,
 150                 .spd_addresses = { 0xa0, 0x00,0x00,0x00 },
 151                 .ts_addresses = { 0x30, 0x00, 0x00, 0x00 },
 152                 .ec_present = 1,
 153                 // 0 = leave channel enabled
 154                 // 1 = disable dimm 0 on channel
 155                 // 2 = disable dimm 1 on channel
 156                 // 3 = disable dimm 0+1 on channel
 157                 .dimm_channel0_disabled = 2,
 158                 .dimm_channel1_disabled = 2,
 159                 .max_ddr3_freq = 1333,
 160                 .usb_port_config = {
 161                         { 1, 0, 0x0080 }, /* P0: Port 0      (OC0) */
 162                         { 1, 1, 0x0080 }, /* P1: Port 1      (OC1) */
 163                         { 1, 0, 0x0040 }, /* P2: MINIPCIE1   (no OC) */
 164                         { 1, 0, 0x0040 }, /* P3: MMC         (no OC) */
 165                         { 0, 0, 0x0000 }, /* P4: Empty */
 166                         { 0, 0, 0x0000 }, /* P5: Empty */
 167                         { 0, 0, 0x0000 }, /* P6: Empty */
 168                         { 0, 0, 0x0000 }, /* P7: Empty */
 169                         { 1, 4, 0x0040 }, /* P8: MINIPCIE2   (no OC) */
 170                         { 0, 4, 0x0000 }, /* P9: Empty */
 171                         { 0, 4, 0x0000 }, /* P10: Empty */
 172                         { 1, 4, 0x0040 }, /* P11: Camera     (no OC) */
 173                         { 0, 4, 0x0000 }, /* P12: Empty */
 174                         { 0, 4, 0x0000 }, /* P13: Empty */
 175                 },
 176         };
 177
 178         typedef const uint8_t spd_blob[256];
 179         spd_blob *spd_data;
 180         size_t spd_file_len;
 181
 182
 183         timestamp_init(get_initial_timestamp());
 184         timestamp_add_now(TS_START_ROMSTAGE);
 185
 186         if (bist == 0)
 187                 enable_lapic();
 188
 189         pch_enable_lpc();
 190
 191         /* Enable GPIOs */
 192         pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
 193         pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
 194         setup_pch_gpios(&lumpy_gpio_map);
 195
 196         console_init();
 197
 198         init_bootmode_straps();
 199
 200         /* Halt if there was a built in self test failure */
 201         report_bist_failure(bist);
 202
 203         if (MCHBAR16(SSKPD) == 0xCAFE) {
 204                 printk(BIOS_DEBUG, "soft reset detected\n");
 205                 boot_mode = 1;
 206
 207                 /* System is not happy after keyboard reset... */
 208                 printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
 209                 outb(0x6, 0xcf9);
 210                 halt();
 211         }
 212
 213         /* Perform some early chipset initialization required
 214          * before RAM initialization can work
 215          */
 216         sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
 217         printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
 218
 219         boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
 220
 221         post_code(0x38);
 222         /* Enable SPD ROMs and DDR-III DRAM */
 223         enable_smbus();
 224
 225         /* Prepare USB controller early in S3 resume */
 226         if (boot_mode == 2)
 227                 enable_usb_bar();
 228
 229         u32 gp_lvl2 = inl(DEFAULT_GPIOBASE + 0x38);
 230         u8 gpio33, gpio41, gpio49;
 231         gpio33 = (gp_lvl2 >> (33-32)) & 1;
 232         gpio41 = (gp_lvl2 >> (41-32)) & 1;
 233         gpio49 = (gp_lvl2 >> (49-32)) & 1;
 234         printk(BIOS_DEBUG, "Memory Straps:\n");
 235         printk(BIOS_DEBUG, " - memory capacity %dGB\n",
 236                 gpio33 ? 2 : 1);
 237         printk(BIOS_DEBUG, " - die revision %d\n",
 238                 gpio41 ? 2 : 1);
 239         printk(BIOS_DEBUG, " - vendor %s\n",
 240                 gpio49 ? "Samsung" : "Other");
 241
 242         int spd_index = 0;
 243
 244         switch ((gpio49 << 2) | (gpio41 << 1) | gpio33) {
 245         case 0: // Other 1G Rev 1
 246                 spd_index = 0;
 247                 break;
 248         case 2: // Other 1G Rev 2
 249                 spd_index = 1;
 250                 break;
 251         case 1: // Other 2G Rev 1
 252         case 3: // Other 2G Rev 2
 253                 spd_index = 2;
 254                 break;
 255         case 4: // Samsung 1G Rev 1
 256                 spd_index = 3;
 257                 break;
 258         case 6: // Samsung 1G Rev 2
 259                 spd_index = 4;
 260                 break;
 261         case 5: // Samsung 2G Rev 1
 262         case 7: // Samsung 2G Rev 2
 263                 spd_index = 5;
 264                 break;
 265         }
 266
 267         spd_data = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
 268                                                 &spd_file_len);
 269         if (!spd_data)
 270                 die("SPD data not found.");
 271         if (spd_file_len < (spd_index + 1) * 256)
 272                 die("Missing SPD data.");
 273         // leave onboard dimm address at f0, and copy spd data there.
 274         memcpy(pei_data.spd_data[0], spd_data[spd_index], 256);
 275
 276         post_code(0x39);
 277         pei_data.boot_mode = boot_mode;
 278         timestamp_add_now(TS_BEFORE_INITRAM);
 279         sdram_initialize(&pei_data);
 280
 281         timestamp_add_now(TS_AFTER_INITRAM);
 282         post_code(0x3a);
 283         /* Perform some initialization that must run before stage2 */
 284         early_pch_init();
 285         post_code(0x3b);
 286
 287         rcba_config();
 288         post_code(0x3c);
 289
 290         quick_ram_check();
 291         post_code(0x3e);
 292
 293         cbmem_was_initted = !cbmem_recovery(boot_mode==2);
 294         if (boot_mode!=2)
 295                 save_mrc_data(&pei_data);
 296
 297         if (boot_mode == 2 && !cbmem_was_initted) {
 298                 /* Failed S3 resume, reset to come up cleanly */
 299                 outb(0x6, 0xcf9);
 300                 halt();
 301         }
 302         northbridge_romstage_finalize(boot_mode==2);
 303         post_code(0x3f);
 304         if (CONFIG_LPC_TPM) {
 305                 init_tpm(boot_mode == 2);
 306         }
 307 }