src/mainboard/pcengines/alix2d/irq_tables.c

   1 /*
   2 * This file is part of the coreboot project.
   3 *
   4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 * GNU General Public License for more details.
  14 */
  15
  16 #include <arch/pirq_routing.h>
  17 #include <console/console.h>
  18 #include <arch/io.h>
  19 #include "southbridge/amd/cs5536/cs5536.h"
  20
  21 /* Platform IRQs */
  22 #define PIRQA 11
  23 #define PIRQB 10
  24 #define PIRQC 11
  25 #define PIRQD 9
  26
  27 /* Map */
  28 #define M_PIRQA (1 << PIRQA)    /* Bitmap of supported IRQs */
  29 #define M_PIRQB (1 << PIRQB)    /* Bitmap of supported IRQs */
  30 #define M_PIRQC (1 << PIRQC)    /* Bitmap of supported IRQs */
  31 #define M_PIRQD (1 << PIRQD)    /* Bitmap of supported IRQs */
  32
  33 /* Link */
  34 #define L_PIRQA 1               /* Means Slot INTx# Connects To Chipset INTA# */
  35 #define L_PIRQB 2               /* Means Slot INTx# Connects To Chipset INTB# */
  36 #define L_PIRQC 3               /* Means Slot INTx# Connects To Chipset INTC# */
  37 #define L_PIRQD 4               /* Means Slot INTx# Connects To Chipset INTD# */
  38
  39 /*
  40  * ALIX.2D3 interrupt wiring.
  41  *
  42  * Devices are:
  43  * 00:01.0 Host bridge [0600]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge [1022:2080] (rev 33)
  44  * 00:01.2 Entertainment encryption device [1010]: Advanced Micro Devices [AMD] Geode LX AES Security Block [1022:2082]
  45  * 00:09.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
  46  * 00:0a.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
  47  * 00:0b.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96)
  48  * 00:0f.0 ISA bridge [0601]: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] (rev 03)
  49  * 00:0f.2 IDE interface [0101]: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] (rev 01)
  50  * 00:0f.4 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] (rev 02)
  51  * 00:0f.5 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] (rev 02)
  52
  53   * The only devices that interrupt are:
  54  *
  55  * What         Device  IRQ     PIN     PIN WIRED TO
  56  * -------------------------------------------------
  57  * AES          00:01.2 0a      01      A       A
  58  * eth0         00:09.0 0b      01      A       B
  59  * eth1         00:0a.0 0b      01      A       C
  60  * eth2         00:0b.0 0b      01      A       D
  61  * mpci         00:0c.0 0a      01      A       A
  62  * mpci         00:0c.0 0b      02      B       B
  63  * usb          00:0f.4 0b      04      D       D
  64  * usb          00:0f.5 0b      04      D       D
  65  *
  66  * The only swizzled interrupts are the ethernet controllers, where INTA is wired to
  67  * interrupt controller lines B, C and D.
  68  */
  69
  70 static const struct irq_routing_table intel_irq_routing_table = {
  71         PIRQ_SIGNATURE,
  72         PIRQ_VERSION,
  73         32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
  74         0x00,                   /* Where the interrupt router lies (bus) */
  75         (0x0F << 3) | 0x0,      /* Where the interrupt router lies (dev) */
  76         0x00,                   /* IRQs devoted exclusively to PCI usage */
  77         0x100B,                 /* Vendor */
  78         0x002B,                 /* Device */
  79         0,                      /* Miniport data */
  80         {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},      /* u8 rfu[11] */
  81         0x00,                   /* Checksum */
  82         {
  83                 /* If you change the number of entries, change CONFIG_IRQ_SLOT_COUNT above! */
  84
  85                 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
  86
  87                 /* CPU */
  88                 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
  89
  90                 /* On-board ethernet (Left) */
  91                 {0x00, (0x09 << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
  92
  93                 /* On-board ethernet (Middle, ALIX.2D3 only) */
  94                 {0x00, (0x0A << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
  95
  96                 /* On-board ethernet (Right) */
  97                 {0x00, (0x0B << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
  98
  99                 /* Mini PCI (slot 1) */
 100                 {0x00, (0x0C << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
 101
 102                 /* Mini PCI (slot 2, ALIX.2D2 only) */
 103                 {0x00, (0x0E << 3) | 0x0, {{L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},
 104
 105                 /* Chipset slots -- f.3 wires to B, and f.4 and f.5 wires to D. */
 106                 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},
 107         }
 108 };
 109
 110 unsigned long write_pirq_routing_table(unsigned long addr)
 111 {
 112         return copy_pirq_routing_table(addr, &intel_irq_routing_table);
 113 }