tree: drop last paragraph of GPL copyright header
[coreboot.git] / src / mainboard / packardbell / ms2290 / smihandler.c
blobeeb55dfdaa61c876e81690daf37ddc6fb6654e53
1 /*
2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <arch/io.h>
18 #include <console/console.h>
19 #include <cpu/x86/smm.h>
20 #include "southbridge/intel/ibexpeak/nvs.h"
21 #include "southbridge/intel/ibexpeak/pch.h"
22 #include "southbridge/intel/ibexpeak/me.h"
23 #include <northbridge/intel/nehalem/nehalem.h>
24 #include <cpu/intel/model_2065x/model_2065x.h>
25 #include <ec/acpi/ec.h>
26 #include <pc80/mc146818rtc.h>
27 #include <delay.h>
29 static void mainboard_smm_init(void)
31 printk(BIOS_DEBUG, "initializing SMI\n");
34 int mainboard_io_trap_handler(int smif)
36 static int smm_initialized;
38 if (!smm_initialized) {
39 mainboard_smm_init();
40 smm_initialized = 1;
43 switch (smif) {
45 default:
46 return 0;
49 /* On success, the IO Trap Handler returns 1
50 * On failure, the IO Trap Handler returns a value != 1 */
51 return 1;
54 void mainboard_smi_gpi(u32 gpi_sts)
58 static int mainboard_finalized = 0;
60 int mainboard_smi_apmc(u8 data)
62 u8 tmp;
63 switch (data) {
64 case APM_CNT_FINALIZE:
65 printk(BIOS_DEBUG, "APMC: FINALIZE\n");
66 if (mainboard_finalized) {
67 printk(BIOS_DEBUG, "APMC#: Already finalized\n");
68 return 0;
71 intel_me_finalize_smm();
72 intel_pch_finalize_smm();
73 intel_nehalem_finalize_smm();
74 intel_model_2065x_finalize_smm();
76 mainboard_finalized = 1;
77 break;
78 case APM_CNT_ACPI_ENABLE:
79 tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
80 tmp &= ~0x03;
81 tmp |= 0x02;
82 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
83 break;
84 case APM_CNT_ACPI_DISABLE:
85 tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
86 tmp &= ~0x03;
87 tmp |= 0x01;
88 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
89 break;
90 default:
91 break;
93 return 0;