src/mainboard/lippert/toucan-af/platform_cfg.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16
  17 #ifndef _PLATFORM_CFG_H_
  18 #define _PLATFORM_CFG_H_
  19
  20 /**
  21  * @def BIOS_SIZE
  22  *      BIOS_SIZE_{1,2,4,8,16}M
  23  *
  24  * In SB800, default ROM size is 1M Bytes, if your platform ROM
  25  * bigger than 1M you have to set the ROM size outside CIMx module and
  26  * before AGESA module get call.
  27  */
  28 #ifndef BIOS_SIZE
  29 #define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
  30 #endif /* BIOS_SIZE */
  31
  32 /**
  33  * @def SPREAD_SPECTRUM
  34  * @brief
  35  *  0 - Disable Spread Spectrum function
  36  *  1 - Enable  Spread Spectrum function
  37  */
  38 #define SPREAD_SPECTRUM                 0
  39
  40 /**
  41  * @def SB_HPET_TIMER
  42  * @brief
  43  *  0 - Disable hpet
  44  *  1 - Enable  hpet
  45  */
  46 #define HPET_TIMER                      1
  47
  48 /**
  49  * @def USB_CONFIG
  50  * @brief bit[0-6] used to control USB
  51  *   0 - Disable
  52  *   1 - Enable
  53  *  Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
  54  *  Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
  55  *  Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
  56  *  Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
  57  *  Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
  58  *  Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
  59  *  Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
  60  */
  61 #define USB_CONFIG              0x0F
  62
  63 /**
  64  * @def PCI_CLOCK_CTRL
  65  * @brief bit[0-4] used for PCI Slots Clock Control,
  66  *   0 - disable
  67  *   1 - enable
  68  *  PCI SLOT 0 define at BIT0
  69  *  PCI SLOT 1 define at BIT1
  70  *  PCI SLOT 2 define at BIT2
  71  *  PCI SLOT 3 define at BIT3
  72  *  PCI SLOT 4 define at BIT4
  73  */
  74 #define PCI_CLOCK_CTRL                  0x1E
  75
  76 /**
  77  * @def SATA_CONTROLLER
  78  * @brief INCHIP Sata Controller
  79  */
  80 #define SATA_CONTROLLER         CIMX_OPTION_ENABLED
  81
  82 /**
  83  * @def SATA_MODE
  84  * @brief INCHIP Sata Controller Mode
  85  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  86  */
  87 #define SATA_MODE                       CONFIG_SB800_SATA_MODE
  88
  89 /**
  90  * @brief INCHIP Sata IDE Controller Mode
  91  */
  92 #define IDE_LEGACY_MODE                 0
  93 #define IDE_NATIVE_MODE                 1
  94
  95 /**
  96  * @def SATA_IDE_MODE
  97  * @brief INCHIP Sata IDE Controller Mode
  98  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  99  */
 100 #define SATA_IDE_MODE                   IDE_LEGACY_MODE
 101
 102 /**
 103  * @def EXTERNAL_CLOCK
 104  * @brief 00/10: Reference clock from crystal oscillator via
 105  *  PAD_XTALI and PAD_XTALO
 106  *
 107  * @def INTERNAL_CLOCK
 108  * @brief 01/11: Reference clock from internal clock through
 109  *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
 110  */
 111 #define EXTERNAL_CLOCK          0x00
 112 #define INTERNAL_CLOCK          0x01
 113
 114 /* NOTE: inagua have to using internal clock,
 115  * otherwise can not detect sata drive
 116  */
 117 #define SATA_CLOCK_SOURCE       INTERNAL_CLOCK
 118
 119 /**
 120  * @def SATA_PORT_MULT_CAP_RESERVED
 121  * @brief 1 ON, 0 0FF
 122  */
 123 #define SATA_PORT_MULT_CAP_RESERVED     1
 124
 125
 126 /**
 127  * @def   AZALIA_AUTO
 128  * @brief Detect Azalia controller automatically.
 129  *
 130  * @def   AZALIA_DISABLE
 131  * @brief Disable Azalia controller.
 132
 133  * @def   AZALIA_ENABLE
 134  * @brief Enable Azalia controller.
 135  */
 136 #define AZALIA_AUTO                     0
 137 #define AZALIA_DISABLE                  1
 138 #define AZALIA_ENABLE                   2
 139
 140 /**
 141  * @brief INCHIP HDA controller
 142  */
 143 #define AZALIA_CONTROLLER               AZALIA_AUTO
 144
 145 /**
 146  * @def AZALIA_PIN_CONFIG
 147  * @brief
 148  *  0 - disable
 149  *  1 - enable
 150  */
 151 #define AZALIA_PIN_CONFIG               1
 152
 153 /**
 154  * @def AZALIA_SDIN_PIN
 155  * @brief
 156  *  SDIN0 is define at BIT0 & BIT1
 157  *   00 - GPIO PIN
 158  *   01 - Reserved
 159  *   10 - As a Azalia SDIN pin
 160  *  SDIN1 is define at BIT2 & BIT3
 161  *  SDIN2 is define at BIT4 & BIT5
 162  *  SDIN3 is define at BIT6 & BIT7
 163  */
 164 #define AZALIA_SDIN_PIN                 0x2A
 165
 166 /**
 167  * @def GPP_CONTROLLER
 168  */
 169 #define GPP_CONTROLLER                  CIMX_OPTION_ENABLED
 170
 171 /**
 172  * @def GPP_CFGMODE
 173  * @brief GPP Link Configuration
 174  * four possible configuration:
 175  *  GPP_CFGMODE_X4000
 176  *  GPP_CFGMODE_X2200
 177  *  GPP_CFGMODE_X2110
 178  *  GPP_CFGMODE_X1111
 179  */
 180 #define GPP_CFGMODE                     GPP_CFGMODE_X1111
 181
 182 /**
 183  * @def NB_SB_GEN2
 184  *    0  - Disable
 185  *    1  - Enable
 186  */
 187 #define NB_SB_GEN2                      TRUE
 188
 189 /**
 190  * @def SB_GPP_GEN2
 191  *    0  - Disable
 192  *    1  - Enable
 193  */
 194 #define SB_GPP_GEN2                     TRUE
 195
 196 /**
 197  * @def SB_GPP_UNHIDE_PORTS
 198  *    TRUE   - ports visible always, even port empty
 199  *    FALSE  - ports invisible if port empty
 200  */
 201 #define SB_GPP_UNHIDE_PORTS             FALSE
 202
 203 /**
 204  * @def   GEC_CONFIG
 205  *    0  - Enable
 206  *    1  - Disable
 207  */
 208 #define GEC_CONFIG                      1
 209
 210 static const CODECENTRY sample_codec_alc886[] = /* Realtek ALC886/8 */
 211 {
 212         /* NID, PinConfig (Verbs 71F..C) */
 213         {0x11, 0x411111F0}, /* NPC */
 214         {0x12, 0x411111F0}, /* DMIC */
 215         {0x14, 0x01214110}, /* FRONT (Port-D) */
 216         {0x15, 0x01011112}, /* SURR (Port-A) */
 217         {0x16, 0x01016111}, /* CEN/LFE (Port-G) */
 218         {0x17, 0x411111F0}, /* SIDESURR (Port-H) */
 219         {0x18, 0x01A19930}, /* MIC1 (Port-B) */
 220         {0x19, 0x411111F0}, /* MIC2 (Port-F) */
 221         {0x1A, 0x0181313F}, /* LINE1 (Port-C) */
 222         {0x1B, 0x411111F0}, /* LINE2 (Port-E) */
 223         {0x1C, 0x411111F0}, /* CD-IN */
 224         {0x1D, 0x40132601}, /* BEEP-IN */
 225         {0x1E, 0x01441120}, /* S/PDIF-OUT */
 226         {0x1F, 0x01C46140}, /* S/PDIF-IN */
 227         {0xff, 0xffffffff} /* end of table */
 228 };
 229
 230 static const CODECTBLLIST codec_tablelist[] =
 231 {
 232         {0x10ec0888, (CODECENTRY*)&sample_codec_alc886[0]},
 233         {0xFFFFFFFF, (CODECENTRY*)0xFFFFFFFFL}
 234 };
 235
 236 /**
 237  * @def AZALIA_OEM_VERB_TABLE
 238  *  Mainboard specific codec verb table list
 239  */
 240 #define AZALIA_OEM_VERB_TABLE           (&codec_tablelist[0])
 241
 242 /* set up an ACPI preferred power management profile */
 243 /*  from acpi.h
 244  *      PM_UNSPECIFIED          = 0,
 245  *      PM_DESKTOP              = 1,
 246  *      PM_MOBILE               = 2,
 247  *      PM_WORKSTATION          = 3,
 248  *      PM_ENTERPRISE_SERVER    = 4,
 249  *      PM_SOHO_SERVER          = 5,
 250  *      PM_APPLIANCE_PC         = 6,
 251  *      PM_PERFORMANCE_SERVER   = 7,
 252  *      PM_TABLET               = 8
 253  */
 254 #define FADT_PM_PROFILE 1
 255
 256 #endif