2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <console/console.h>
18 #include <device/device.h>
19 #include <device/pci.h>
21 #include <cpu/x86/msr.h>
22 #include <device/pci_def.h>
23 #include <southbridge/amd/sb800/sb800.h>
24 #include <arch/acpi.h>
25 #include <northbridge/amd/agesa/BiosCallOuts.h>
26 #include <cpu/amd/agesa/s3_resume.h>
27 #include <cpu/amd/mtrr.h>
28 #include "SBPLATFORM.h"
29 #include "OEM.h" /* SMBUS0_BASE_ADDRESS */
30 #include <southbridge/amd/cimx/sb800/gpio_oem.h>
33 #define SIO_RUNTIME_BASE 0x0E00
34 static const u16 sio_init_table
[] = { // hi=offset, lo=value
35 0x4BA0, // GP1x: COM1/2 control = RS232, no term, max 115200
36 0x2300, // GP10: COM1 termination = push/pull output
37 0x2400, // GP11: COM2 termination = push/pull output
38 0x2500, // GP12: COM1 RS485 mode = push/pull output
39 0x2600, // GP13: COM2 RS485 mode = push/pull output
40 0x2700, // GP14: COM1 speed A = push/pull output
41 0x2900, // GP15: COM1 speed B = push/pull output
42 0x2A00, // GP16: COM2 speed A = push/pull output
43 0x2B00, // GP17: COM2 speed B = push/pull output
45 0x3904, // GP36 = KBDRST# function
47 0x4E74, // GP4x: Ethernet enable = on
48 0x6E84, // GP44: Ethernet enable = open drain output
50 // GP5x = COM2 function instead of GPIO
51 0x3F05, 0x4005, 0x4105, 0x4204, 0x4305, 0x4404, 0x4505, 0x4604,
53 0x470C, // GP60 = WDT function
54 0x5E00, // LED2: Live LED = off
55 0x4884, // GP61: Live LED = LED2 function
57 0x5038, // GP6x: USB power = 3x on
58 0x5580, // GP63: USB power 0/1 = open drain output
59 0x5680, // GP64: USB power 2/3 = open drain output
60 0x5780, // GP65: USB power 4/5 = open drain output
63 /* Write data block to slave on SMBUS0. */
64 #define SMB0_STATUS ((SMBUS0_BASE_ADDRESS) + 0)
65 #define SMB0_CONTROL ((SMBUS0_BASE_ADDRESS) + 2)
66 #define SMB0_HOSTCMD ((SMBUS0_BASE_ADDRESS) + 3)
67 #define SMB0_ADDRESS ((SMBUS0_BASE_ADDRESS) + 4)
68 #define SMB0_DATA0 ((SMBUS0_BASE_ADDRESS) + 5)
69 #define SMB0_BLOCKDATA ((SMBUS0_BASE_ADDRESS) + 7)
70 static int smb_write_blk(u8 slave
, u8 command
, u8 length
, const u8
*data
)
72 __outbyte(SMB0_STATUS
, 0x1E); // clear error status
73 __outbyte(SMB0_ADDRESS
, slave
& ~1); // slave addr + direction=out
74 __outbyte(SMB0_HOSTCMD
, command
); // or destination offset
75 __outbyte(SMB0_DATA0
, length
); // sent before data
76 __inbyte(SMB0_CONTROL
); // reset block data array
78 __outbyte(SMB0_BLOCKDATA
, *(data
++));
79 __outbyte(SMB0_CONTROL
, 0x54); // execute block write, no IRQ
81 while (__inbyte(SMB0_STATUS
) == 0x01) ; // busy, no errors
82 return __inbyte(SMB0_STATUS
) ^ 0x02; // 0x02 = completed, no errors
85 static void init(struct device
*dev
)
87 volatile u8
*spi_base
; // base addr of Hudson's SPI host controller
89 printk(BIOS_DEBUG
, CONFIG_MAINBOARD_PART_NUMBER
" ENTER %s\n", __func__
);
91 /* Init Hudson GPIOs. */
92 printk(BIOS_DEBUG
, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE
+GPIO_BASE
);
93 FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices
94 FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed
95 FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# = input (int. PU)
96 FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0
97 FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups
99 FCH_GPIO ( 57) = 0x28;
101 FCH_GPIO ( 58) = 0x28;
102 FCH_IOMUX( 96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU)
103 FCH_IOMUX( 52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector
104 FCH_IOMUX( 61) = 2; // default to inputs with int. PU
112 if (!fch_gpio_state(197)) // just in case anyone cares
113 printk(BIOS_INFO
, "BIOS_DEFAULTS jumper is present.\n");
114 printk(BIOS_INFO
, "Board revision ID: %u\n",
115 fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56));
117 /* Init SIO GPIOs. */
118 printk(BIOS_DEBUG
, "Init SIO GPIOs @ 0x%04x\n", SIO_RUNTIME_BASE
);
119 for (i
= 0; i
< ARRAY_SIZE(sio_init_table
); i
++) {
120 u16 val
= sio_init_table
[i
];
121 outb((u8
)val
, SIO_RUNTIME_BASE
+ (val
>> 8));
124 /* Lower SPI speed from default 66 to 22 MHz for SST 25VF032B */
125 spi_base
= (u8
*)((uintptr_t)pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x14, 3)), 0xA0) & 0xFFFFFFE0);
126 spi_base
[0x0D] = (spi_base
[0x0D] & ~0x30) | 0x20; // NormSpeed in SPI_Cntrl1 register
128 /* Notify the SMC we're alive and kicking, or after a while it will
129 * effect a power cycle and switch to the alternate BIOS chip.
130 * Should be done as late as possible. */
131 printk(BIOS_INFO
, "Sending BIOS alive message\n");
132 const u8 i_am_alive
[] = { 0x03 };
133 if ((i
= smb_write_blk(0x50, 0x25, sizeof(i_am_alive
), i_am_alive
)))
134 printk(BIOS_ERR
, "smb_write_blk failed: %d\n", i
);
136 printk(BIOS_DEBUG
, CONFIG_MAINBOARD_PART_NUMBER
" EXIT %s\n", __func__
);
139 void set_pcie_reset(void);
140 void set_pcie_dereset(void);
146 void set_pcie_reset(void)
152 * mainboard specific SB CIMx callback
154 void set_pcie_dereset(void)
159 /**********************************************
160 * Enable the dedicated functions of the board.
161 **********************************************/
162 static void mainboard_enable(device_t dev
)
164 printk(BIOS_INFO
, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER
" Enable.\n");
165 dev
->ops
->init
= init
;
167 /* enable GPP CLK0 */
168 /* disable GPP CLK1 thru SLT_GFX_CLK */
169 u8
*misc_mem_clk_cntrl
= (u8
*)(ACPI_MMIO_BASE
+ MISC_BASE
);
170 write8(misc_mem_clk_cntrl
+ 0, 0x0F);
171 write8(misc_mem_clk_cntrl
+ 1, 0x00);
172 write8(misc_mem_clk_cntrl
+ 2, 0x00);
173 write8(misc_mem_clk_cntrl
+ 3, 0x00);
174 write8(misc_mem_clk_cntrl
+ 4, 0x00);
177 * Initialize ASF registers to an arbitrary address because someone
178 * long ago set things up this way inside the SPD read code. The
179 * SPD read code has been made generic and moved out of the board
180 * directory, so the ASF init is being done here.
182 pm_iowrite(0x29, 0x80);
183 pm_iowrite(0x28, 0x61);
186 struct chip_operations mainboard_ops
= {
187 .enable_dev
= mainboard_enable
,