2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <console/console.h>
18 #include <device/device.h>
23 #include "southbridge/intel/i82801gx/i82801gx.h"
24 #include <superio/nsc/pc87392/pc87392.h>
26 static void dlpc_write_register(int reg
, int value
)
32 static u8
dlpc_read_register(int reg
)
38 static void dock_write_register(int reg
, int value
)
44 static u8
dock_read_register(int reg
)
50 static void dlpc_gpio_set_mode(int port
, int mode
)
52 dlpc_write_register(0xf0, port
);
53 dlpc_write_register(0xf1, mode
);
56 static void dock_gpio_set_mode(int port
, int mode
, int irq
)
58 dock_write_register(0xf0, port
);
59 dock_write_register(0xf1, mode
);
60 dock_write_register(0xf2, irq
);
63 static void dlpc_gpio_init(void)
65 /* Select GPIO module */
66 dlpc_write_register(0x07, 0x07);
67 /* GPIO Base Address 0x1680 */
68 dlpc_write_register(0x60, 0x16);
69 dlpc_write_register(0x61, 0x80);
72 dlpc_write_register(0x30, 0x01);
74 dlpc_gpio_set_mode(0x00, 3);
75 dlpc_gpio_set_mode(0x01, 3);
76 dlpc_gpio_set_mode(0x02, 0);
77 dlpc_gpio_set_mode(0x03, 3);
78 dlpc_gpio_set_mode(0x04, 4);
79 dlpc_gpio_set_mode(0x20, 4);
80 dlpc_gpio_set_mode(0x21, 4);
81 dlpc_gpio_set_mode(0x23, 4);
88 /* Enable 14.318MHz CLK on CLKIN */
89 dlpc_write_register(0x29, 0xa0);
90 while(!(dlpc_read_register(0x29) & 0x10) && timeout
--)
96 /* Select DLPC module */
97 dlpc_write_register(0x07, 0x19);
98 /* DLPC Base Address 0x164c */
99 dlpc_write_register(0x60, 0x16);
100 dlpc_write_register(0x61, 0x4c);
102 dlpc_write_register(0x30, 0x01);
109 int dock_connect(void)
117 while(!(inb(0x164c) & 8) && timeout
--)
121 /* docking failed, disable DLPC switch */
123 dlpc_write_register(0x30, 0x00);
127 /* Assert D_PLTRST# */
130 /* Deassert D_PLTRST# */
135 /* startup 14.318MHz Clock */
136 dock_write_register(0x29, 0x06);
137 /* wait until clock is settled */
139 while(!(dock_read_register(0x29) & 0x08) && timeout
--)
150 dock_write_register(0x24, 0x37);
152 /* PNF active HIGH */
153 dock_write_register(0x25, 0xa0);
156 dock_write_register(0x26, 0x01);
158 /* Enable GPIO IRQ to #SMI */
159 dock_write_register(0x28, 0x02);
162 dock_write_register(0x07, 0x07);
164 /* set base address */
165 dock_write_register(0x60, 0x16);
166 dock_write_register(0x61, 0x20);
169 dock_gpio_set_mode(0x00, PC87392_GPIO_PIN_DEBOUNCE
|
170 PC87392_GPIO_PIN_PULLUP
, 0x00);
172 dock_gpio_set_mode(0x01, PC87392_GPIO_PIN_DEBOUNCE
|
173 PC87392_GPIO_PIN_PULLUP
,
174 PC87392_GPIO_PIN_TRIGGERS_SMI
);
176 dock_gpio_set_mode(0x02, PC87392_GPIO_PIN_PULLUP
, 0x00);
177 dock_gpio_set_mode(0x03, PC87392_GPIO_PIN_PULLUP
, 0x00);
178 dock_gpio_set_mode(0x04, PC87392_GPIO_PIN_PULLUP
, 0x00);
179 dock_gpio_set_mode(0x05, PC87392_GPIO_PIN_PULLUP
, 0x00);
180 dock_gpio_set_mode(0x06, PC87392_GPIO_PIN_PULLUP
, 0x00);
181 dock_gpio_set_mode(0x07, PC87392_GPIO_PIN_PULLUP
, 0x02);
183 dock_gpio_set_mode(0x10, PC87392_GPIO_PIN_DEBOUNCE
|
184 PC87392_GPIO_PIN_PULLUP
,
185 PC87392_GPIO_PIN_TRIGGERS_SMI
);
187 dock_gpio_set_mode(0x11, PC87392_GPIO_PIN_PULLUP
, 0x00);
188 dock_gpio_set_mode(0x12, PC87392_GPIO_PIN_PULLUP
, 0x00);
189 dock_gpio_set_mode(0x13, PC87392_GPIO_PIN_PULLUP
, 0x00);
190 dock_gpio_set_mode(0x14, PC87392_GPIO_PIN_PULLUP
, 0x00);
191 dock_gpio_set_mode(0x15, PC87392_GPIO_PIN_PULLUP
, 0x00);
192 dock_gpio_set_mode(0x16, PC87392_GPIO_PIN_PULLUP
|
193 PC87392_GPIO_PIN_OE
, 0x00);
195 dock_gpio_set_mode(0x17, PC87392_GPIO_PIN_PULLUP
, 0x00);
197 dock_gpio_set_mode(0x20, PC87392_GPIO_PIN_TYPE_PUSH_PULL
|
198 PC87392_GPIO_PIN_OE
, 0x00);
200 dock_gpio_set_mode(0x21, PC87392_GPIO_PIN_TYPE_PUSH_PULL
|
201 PC87392_GPIO_PIN_OE
, 0x00);
203 dock_gpio_set_mode(0x22, PC87392_GPIO_PIN_PULLUP
, 0x00);
204 dock_gpio_set_mode(0x23, PC87392_GPIO_PIN_PULLUP
, 0x00);
205 dock_gpio_set_mode(0x24, PC87392_GPIO_PIN_PULLUP
, 0x00);
206 dock_gpio_set_mode(0x25, PC87392_GPIO_PIN_PULLUP
, 0x00);
207 dock_gpio_set_mode(0x26, PC87392_GPIO_PIN_PULLUP
, 0x00);
208 dock_gpio_set_mode(0x27, PC87392_GPIO_PIN_PULLUP
, 0x00);
210 dock_gpio_set_mode(0x30, PC87392_GPIO_PIN_PULLUP
, 0x00);
211 dock_gpio_set_mode(0x31, PC87392_GPIO_PIN_PULLUP
, 0x00);
212 dock_gpio_set_mode(0x32, PC87392_GPIO_PIN_PULLUP
, 0x00);
213 dock_gpio_set_mode(0x33, PC87392_GPIO_PIN_PULLUP
, 0x00);
214 dock_gpio_set_mode(0x34, PC87392_GPIO_PIN_PULLUP
, 0x00);
216 dock_gpio_set_mode(0x35, PC87392_GPIO_PIN_PULLUP
|
217 PC87392_GPIO_PIN_OE
, 0x00);
219 dock_gpio_set_mode(0x36, PC87392_GPIO_PIN_PULLUP
, 0x00);
220 dock_gpio_set_mode(0x37, PC87392_GPIO_PIN_PULLUP
, 0x00);
223 dock_write_register(0x30, 0x01);
230 /* Enable USB and Ultrabay power */
233 dock_write_register(0x07, 0x03);
234 dock_write_register(0x30, 0x01);
238 void dock_disconnect(void)
240 printk(BIOS_DEBUG
, "%s enter\n", __func__
);
241 /* disconnect LPC bus */
245 /* Assert PLTRST and DLPCPD */
249 /* disable Ultrabay and USB Power */
253 printk(BIOS_DEBUG
, "%s finish\n", __func__
);
256 int dock_present(void)
258 return !((inb(DEFAULT_GPIOBASE
+ 0x0c) >> 13) & 1);
261 int dock_ultrabay_device_present(void)
263 return inb(0x1621) & 0x02 ? 0 : 1;