src/mainboard/lenovo/x230/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2010 coresystems GmbH
   5  * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
   6  * Copyright (C) 2014 Vladimir Serbinenko
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <stdint.h>
  19 #include <string.h>
  20 #include <lib.h>
  21 #include <timestamp.h>
  22 #include <arch/byteorder.h>
  23 #include <arch/io.h>
  24 #include <device/pci_def.h>
  25 #include <device/pnp_def.h>
  26 #include <cpu/x86/lapic.h>
  27 #include <pc80/mc146818rtc.h>
  28 #include <arch/acpi.h>
  29 #include <cbmem.h>
  30 #include <console/console.h>
  31 #include <northbridge/intel/sandybridge/sandybridge.h>
  32 #include <northbridge/intel/sandybridge/raminit_native.h>
  33 #include <southbridge/intel/bd82x6x/pch.h>
  34 #include <southbridge/intel/bd82x6x/gpio.h>
  35 #include <arch/cpu.h>
  36 #include <cpu/x86/msr.h>
  37 #include <cbfs.h>
  38
  39 void pch_enable_lpc(void)
  40 {
  41         /* X230 EC Decode Range Port60/64, Port62/66 */
  42         /* Enable EC, PS/2 Keyboard/Mouse */
  43         pci_write_config16(PCH_LPC_DEV, LPC_EN,
  44                            CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
  45                            COMA_LPC_EN);
  46
  47         pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
  48         pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
  49         pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
  50
  51         pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
  52
  53         pci_write_config32(PCH_LPC_DEV, 0xac,
  54                            0x80010000);
  55 }
  56
  57 void rcba_config(void)
  58 {
  59         /* Disable unused devices (board specific) */
  60         RCBA32(FD) = 0x17f81fe3;
  61         RCBA32(BUC) = 0;
  62 }
  63
  64 const struct southbridge_usb_port mainboard_usb_ports[] = {
  65         { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */
  66         { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */
  67         { 1, 1, 3 }, /* P2: dock, OC 3 */
  68         { 1, 1, -1 }, /* P3: wwan, no OC */
  69         { 1, 1, -1 }, /* P4: Wacom tablet on X230t, otherwise empty */
  70         { 1, 1, -1 }, /* P5: Expresscard, no OC */
  71         { 0, 0, -1 }, /* P6: Empty */
  72         { 1, 2, -1 }, /* P7: dock, no OC */
  73         { 1, 0, -1 },
  74         { 1, 2, 5 }, /* P9: Right (EHCI debug), OC 5 */
  75         { 1, 1, -1 }, /* P10: fingerprint reader, no OC */
  76         { 1, 1, -1 }, /* P11: bluetooth, no OC. */
  77         { 1, 1, -1 }, /* P12: wlan, no OC */
  78         { 1, 1, -1 }, /* P13: webcam, no OC */
  79 };
  80
  81 void mainboard_get_spd(spd_raw_data *spd) {
  82         read_spd (&spd[0], 0x50);
  83         read_spd (&spd[2], 0x51);
  84 }