src/mainboard/lenovo/x201/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2009 coresystems GmbH
   5  * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
   6  * Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; version 2 of
  11  * the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 /* __PRE_RAM__ means: use "unsigned" for device, not a struct.  */
  20
  21 #include <stdint.h>
  22 #include <string.h>
  23 #include <arch/io.h>
  24 #include <device/pci_def.h>
  25 #include <device/pnp_def.h>
  26 #include <cpu/x86/lapic.h>
  27 #include <lib.h>
  28 #include <pc80/mc146818rtc.h>
  29 #include <console/console.h>
  30 #include <cpu/x86/bist.h>
  31 #include <ec/acpi/ec.h>
  32 #include <delay.h>
  33 #include <timestamp.h>
  34 #include <arch/acpi.h>
  35 #include <cbmem.h>
  36 #include <tpm.h>
  37
  38 #include "gpio.h"
  39 #include "dock.h"
  40 #include "arch/early_variables.h"
  41 #include <southbridge/intel/ibexpeak/pch.h>
  42 #include <northbridge/intel/nehalem/nehalem.h>
  43
  44 #include <northbridge/intel/nehalem/raminit.h>
  45 #include <southbridge/intel/ibexpeak/me.h>
  46
  47 static void pch_enable_lpc(void)
  48 {
  49         /* X201 EC Decode Range Port60/64, Port62/66 */
  50         /* Enable EC, PS/2 Keyboard/Mouse */
  51         pci_write_config16(PCH_LPC_DEV, LPC_EN,
  52                            CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
  53                            COMA_LPC_EN | GAMEL_LPC_EN);
  54
  55         pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
  56         pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
  57         pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681);
  58         pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001);
  59
  60         pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
  61
  62         pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0);
  63         pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8);
  64
  65         pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
  66                           (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1);
  67
  68         pci_write_config32(PCH_LPC_DEV, ETR3,
  69                            pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR);
  70 }
  71
  72 static void rcba_config(void)
  73 {
  74         southbridge_configure_default_intmap();
  75
  76         static const u32 rcba_dump3[] = {
  77                 /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000,
  78                 /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000,
  79                 /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  80                 /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000,
  81                 /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  82                 /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  83                 /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000,
  84                 /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  85                 /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  86                 /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000,
  87                 /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  88                 /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b,
  89                 /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000,
  90                 /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  91                 /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  92                 /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000,
  93                 /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f,
  94                 /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000,
  95                 /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  96                 /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000,
  97                 /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  98                 /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  99                 /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 100                 /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 101                 /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 102                 /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 103                 /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 104                 /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 105                 /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 106                 /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 107                 /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 108                 /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b,
 109                 /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b,
 110                 /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f,
 111                 /* 3530 */ 0x20000557, 0x2000055f, 0x00000000, 0x00000000,
 112                 /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 113                 /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 114                 /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052,
 115                 /* 3570 */ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630,
 116                 /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 117                 /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 118                 /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000,
 119                 /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 120                 /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 121                 /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 122                 /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 123                 /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 124                 /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001,
 125                 /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000,
 126                 /* 3600 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 127                 /* 3610 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 128                 /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 129                 /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 130                 /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 131                 /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 132                 /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 133                 /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 134                 /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 135                 /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 136                 /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 137                 /* 36b0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000,
 138                 /* 36c0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000,
 139                 /* 36d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 140                 /* 36e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 141                 /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 142                 /* 3710 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000,
 143         };
 144         unsigned i;
 145         for (i = 0; i < sizeof(rcba_dump3) / 4; i++) {
 146                 RCBA32(4 * i + 0x3310) = rcba_dump3[i];
 147                 (void)RCBA32(4 * i + 0x3310);
 148         }
 149 }
 150
 151 static inline void write_acpi32(u32 addr, u32 val)
 152 {
 153         outl(val, DEFAULT_PMBASE | addr);
 154 }
 155
 156 static inline void write_acpi16(u32 addr, u16 val)
 157 {
 158         outw(val, DEFAULT_PMBASE | addr);
 159 }
 160
 161 static inline u32 read_acpi32(u32 addr)
 162 {
 163         return inl(DEFAULT_PMBASE | addr);
 164 }
 165
 166 static void set_fsb_frequency(void)
 167 {
 168         u8 block[5];
 169         u16 fsbfreq = 62879;
 170         smbus_block_read(0x69, 0, 5, block);
 171         block[0] = fsbfreq;
 172         block[1] = fsbfreq >> 8;
 173
 174         smbus_block_write(0x69, 0, 5, block);
 175 }
 176
 177 #include <cpu/intel/romstage.h>
 178 void main(unsigned long bist)
 179 {
 180         u32 reg32;
 181         int s3resume = 0;
 182         const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 };
 183
 184         timestamp_init(timestamp_get());
 185
 186         timestamp_add_now(TS_START_ROMSTAGE);
 187
 188         if (bist == 0)
 189                 enable_lapic();
 190
 191         nehalem_early_initialization(NEHALEM_MOBILE);
 192
 193         pch_enable_lpc();
 194
 195         /* Enable USB Power. We need to do it early for usbdebug to work. */
 196         ec_set_bit(0x3b, 4);
 197
 198         /* Enable GPIOs */
 199         pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
 200         pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
 201
 202         setup_pch_gpios(&x201_gpio_map);
 203
 204
 205         /* This should probably go away. Until now it is required
 206          * and mainboard specific
 207          */
 208         rcba_config();
 209
 210         console_init();
 211
 212         /* Halt if there was a built in self test failure */
 213         report_bist_failure(bist);
 214
 215         /* Read PM1_CNT */
 216         reg32 = inl(DEFAULT_PMBASE + 0x04);
 217         printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 218         if (((reg32 >> 10) & 7) == 5) {
 219                 u8 reg8;
 220                 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 221                 printk(BIOS_DEBUG, "a2: %02x\n", reg8);
 222                 if (!(reg8 & 0x20)) {
 223                         outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 224                         printk(BIOS_DEBUG, "Bad resume from S3 detected.\n");
 225                 } else {
 226                         if (acpi_s3_resume_allowed()) {
 227                                 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
 228                                 s3resume = 1;
 229                         } else {
 230                                 printk(BIOS_DEBUG,
 231                                        "Resume from S3 detected, but disabled.\n");
 232                         }
 233                 }
 234         }
 235
 236         /* Enable SMBUS. */
 237         enable_smbus();
 238
 239         outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20,
 240              DEFAULT_GPIOBASE | 0x3a);
 241         outb(0x50, 0x15ec);
 242         outb(inb(0x15ee) & 0x70, 0x15ee);
 243
 244         write_acpi16(0x2, 0x0);
 245         write_acpi32(0x28, 0x0);
 246         write_acpi32(0x2c, 0x0);
 247         if (!s3resume) {
 248                 read_acpi32(0x4);
 249                 read_acpi32(0x20);
 250                 read_acpi32(0x34);
 251                 write_acpi16(0x0, 0x900);
 252                 write_acpi32(0x20, 0xffff7ffe);
 253                 write_acpi32(0x34, 0x56974);
 254                 pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
 255                                   pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2);
 256         }
 257
 258         early_thermal_init();
 259
 260         timestamp_add_now(TS_BEFORE_INITRAM);
 261
 262         chipset_init(s3resume);
 263
 264         set_fsb_frequency();
 265
 266         raminit(s3resume, spd_addrmap);
 267
 268         timestamp_add_now(TS_AFTER_INITRAM);
 269
 270         intel_early_me_status();
 271
 272         if (s3resume) {
 273                 /* Clear SLP_TYPE. This will break stage2 but
 274                  * we care for that when we get there.
 275                  */
 276                 reg32 = inl(DEFAULT_PMBASE + 0x04);
 277                 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 278         }
 279
 280 #if CONFIG_HAVE_ACPI_RESUME
 281         /* If there is no high memory area, we didn't boot before, so
 282          * this is not a resume. In that case we just create the cbmem toc.
 283          */
 284         if (s3resume) {
 285                 void *resume_backup_memory;
 286
 287                 resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 288
 289                 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
 290                  * through stage 2. We could keep stuff like stack and heap in high tables
 291                  * memory completely, but that's a wonderful clean up task for another
 292                  * day.
 293                  */
 294                 if (resume_backup_memory)
 295                         memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE,
 296                                HIGH_MEMORY_SAVE);
 297
 298                 /* Magic for S3 resume */
 299                 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
 300         } else {
 301                 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
 302                 quick_ram_check();
 303         }
 304 #endif
 305
 306 #if CONFIG_LPC_TPM
 307         init_tpm(s3resume);
 308 #endif
 309 }