src/mainboard/jetway/nf81-t56n-lf/mptable.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2014 Sage Electronic Engineering, LLC.
   6  * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18
  19 #include <arch/io.h>
  20 #include <arch/ioapic.h>
  21 #include <arch/smp/mpspec.h>
  22 #include <console/console.h>
  23 #include <cpu/amd/amdfam14.h>
  24 #include <device/pci.h>
  25 #include <drivers/generic/ioapic/chip.h>
  26 #include <stdint.h>
  27 #include <string.h>
  28
  29 #include <southbridge/amd/common/amd_pci_util.h>
  30 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
  31
  32
  33 static void *smp_write_config_table(void *v)
  34 {
  35         struct mp_config_table *mc;
  36         int bus_isa;
  37
  38         /*
  39          * By the time this function gets called, the IOAPIC registers
  40          * have been written so they can be read to get the correct
  41          * APIC ID and Version
  42          */
  43         u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
  44         u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
  45
  46         /* Intialize the MP_Table */
  47         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  48
  49         mptable_init(mc, LOCAL_APIC_ADDR);
  50
  51         /*
  52          * Type 0: Processor Entries:
  53          * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
  54          * CPU Signature (Stepping, Model, Family),
  55          * Feature Flags
  56          */
  57         smp_write_processors(mc);
  58
  59         /*
  60          * Type 1: Bus Entries:
  61          * Bus ID, Bus Type
  62          */
  63         mptable_write_buses(mc, NULL, &bus_isa);
  64
  65         /*
  66          * Type 2: I/O APICs:
  67          * APIC ID, Version, APIC Flags:EN, Address
  68          */
  69         smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
  70
  71         /*
  72          * Type 3: I/O Interrupt Table Entries:
  73          * Int Type, Int Polarity, Int Level, Source Bus ID,
  74          * Source Bus IRQ, Dest APIC ID, Dest PIN#
  75          */
  76         mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
  77
  78         /* PCI interrupts are level triggered, and are
  79          * associated with a specific bus/device/function tuple.
  80          */
  81 #define PCI_INT(bus, dev, fn, pin) \
  82                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
  83
  84         /* APU Internal Graphic Device */
  85         PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
  86         PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
  87
  88         /* SMBUS / ACPI */
  89         PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
  90
  91         /* Southbridge HD Audio */
  92         PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
  93
  94         /* LPC */
  95         PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
  96
  97         /* USB */
  98         PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
  99         PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
 100         PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
 101         PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
 102         PCI_INT(0x0, 0x14, 0x5, intr_data_ptr[PIRQ_OHCI4]);
 103
 104          /* IDE */
 105         PCI_INT(0x0, 0x14, 0x1, intr_data_ptr[PIRQ_IDE]);
 106
 107         /* SATA */
 108         PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
 109
 110         /* On-board NIC & Slot PCIE. */
 111         PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);  /* Use INTE */
 112         PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]);  /* Use INTE */
 113
 114         /* PCI slots */
 115         device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
 116         if (dev && dev->enabled) {
 117                 u8 bus_pci = dev->link_list->secondary;
 118                 /* PCI_SLOT 0 */
 119                 PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);      /* INTA -> INTE */
 120                 PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);      /* INTB -> INTF */
 121                 PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);      /* INTC -> INTG */
 122                 PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);      /* INTD -> INTH */
 123         }
 124
 125         /* On-board Realtek NIC 2. (PCIe PortA) */
 126         PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_E]); /* INTA -> INTE */
 127         /* PCIe PortB */
 128         PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_F]); /* INTB -> INTF */
 129         /* PCIe PortC */
 130         PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_G]); /* INTC -> INTG */
 131         /* PCIe PortD */
 132         PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_H]); /* INTD -> INTH */
 133
 134         /*Local Ints:    Type   Polarity        Trigger  Bus ID  IRQ    APIC ID PIN# */
 135 #define IO_LOCAL_INT(type, intr, apicid, pin) \
 136                 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 137
 138         IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
 139         IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
 140         /* There is no extension information... */
 141
 142         /* Compute the checksums */
 143         return mptable_finalize(mc);
 144 }
 145
 146 unsigned long write_smp_table(unsigned long addr)
 147 {
 148         void *v;
 149         v = smp_write_floating_table(addr, 0);  /* ADDR, Enable Virtual Wire */
 150         return (unsigned long)smp_write_config_table(v);
 151 }