src/mainboard/intel/wtm2/gpio.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef INTEL_WTM2_GPIO_H
  17 #define INTEL_WTM2_GPIO_H
  18
  19 #include <soc/gpio.h>
  20
  21 static const struct gpio_config mainboard_gpio_config[] = {
  22         PCH_GPIO_NATIVE,        /* 0: LPSS_UART1_RXD */
  23         PCH_GPIO_NATIVE,        /* 1: LPSS_UART1_TXD */
  24         PCH_GPIO_NATIVE,        /* 2: LPSS_UART1_RTS_N_R */
  25         PCH_GPIO_NATIVE,        /* 3: LPSS_UART1_CTS_N */
  26         PCH_GPIO_NATIVE,        /* 4: LPSS_I2C0_SDA_R */
  27         PCH_GPIO_NATIVE,        /* 5: LPSS_I2C0_SCL */
  28         PCH_GPIO_NATIVE,        /* 6: LPSS_I2C1_SDA */
  29         PCH_GPIO_NATIVE,        /* 7: LPSS_I2C1_SCL */
  30         PCH_GPIO_UNUSED,        /* 8: NGFF_SLTA_WIFI_WAKE_N */
  31         PCH_GPIO_UNUSED,        /* 9: ACCEL_INT2_MCP */
  32         PCH_GPIO_ACPI_SCI,      /* 10: SMC_RUNTIME_SCI_N */
  33         PCH_GPIO_UNUSED,        /* 11: AMB_THRM_R_N */
  34         PCH_GPIO_NATIVE,        /* 12: PM_LANPHY_ENABLE */
  35         PCH_GPIO_OUT_HIGH,      /* 13: USB32_P0_PWREN */
  36         PCH_GPIO_IRQ_EDGE,      /* 14: SH_INT_ACCEL_DRDY_USB_INT_N */
  37         PCH_GPIO_OUT_HIGH,      /* 15: LAN_PWREN_N */
  38         PCH_GPIO_OUT_HIGH,      /* 16: LAN_RST_N */
  39         PCH_GPIO_OUT_LOW,       /* 17: CRIT_TEMP_REP_R_N */
  40         PCH_GPIO_UNUSED,        /* 18: TBT_FORCE_PWR */
  41         PCH_GPIO_INPUT,         /* 19: EC_IN_RW */
  42         PCH_GPIO_NATIVE,        /* 20: CK_REQ_P2_NGFFSLTA_N_R */
  43         PCH_GPIO_NATIVE,        /* 21: CK_PCIE_LAN_REQ_N */
  44         PCH_GPIO_NATIVE,        /* 22: CK_REQ_P4_TBT_N */
  45         PCH_GPIO_NATIVE,        /* 23: CK_REQ_P5_N */
  46         PCH_GPIO_OUT_LOW,       /* 24: ME_PG_LED */
  47         PCH_GPIO_INPUT,         /* 25: USB_WAKEOUT_N */
  48         PCH_GPIO_IRQ_EDGE,      /* 26: NFC_IRQ_MGP5 */
  49         PCH_GPIO_ACPI_SCI,      /* 27: SMC_WAKE_SCI_N */
  50         PCH_GPIO_OUT_LOW,       /* 28: PCH_NFC_RESET */
  51         PCH_GPIO_NATIVE,        /* 29: PCH_SLP_WLAN_N */
  52         PCH_GPIO_NATIVE,        /* 30: SUS_PWR_ACK_R */
  53         PCH_GPIO_NATIVE,        /* 31: AC_PRESENT_R */
  54         PCH_GPIO_NATIVE,        /* 32: PM_CKRUN_N */
  55         PCH_GPIO_OUT_LOW,       /* 33: SATA0_PHYSLP */
  56         PCH_GPIO_INPUT,         /* 34: ESATA_DET_N */
  57         PCH_GPIO_INPUT,         /* 35: SATA_DIRECT_PRSNT_R_N */
  58         PCH_GPIO_INPUT,         /* 36: NGFF_SSD_SATA2_PCIE1_DET_N */
  59         PCH_GPIO_INPUT,         /* 37: NGFF_SSD_SATA3_PCIE0_DET_N */
  60         PCH_GPIO_OUT_LOW,       /* 38: SATA1_PHYSLP_DIRECT */
  61         PCH_GPIO_ACPI_SMI,      /* 39: SMC_EXTSMI_N_R */
  62         PCH_GPIO_NATIVE,        /* 40: USB_OC_0_1_R_N */
  63         PCH_GPIO_NATIVE,        /* 41: USB_OC_2_6_R_N */
  64         PCH_GPIO_INPUT,         /* 42: TBT_CIO_PLUG_SMI_N_R */
  65         PCH_GPIO_OUT_HIGH,      /* 43: USB32_P1_PWREN */
  66         PCH_GPIO_INPUT,         /* 44: SENSOR_HUB_RST_N */
  67         PCH_GPIO_INPUT,         /* 45: GYRO_INT2_MCP_R */
  68         PCH_GPIO_OUT_HIGH,      /* 46: SNSR_HUB_PWREN */
  69         PCH_GPIO_IRQ_EDGE,      /* 47: SPI_TPM_HDR_IRQ_N */
  70         PCH_GPIO_OUT_HIGH,      /* 48: PCIE_TBT_RST_N */
  71         PCH_GPIO_INPUT,         /* 49: COMBO_JD */
  72         PCH_GPIO_IRQ_EDGE,      /* 50: TOUCH_PANEL_INTR_N */
  73         PCH_GPIO_OUT_HIGH,      /* 51: PCH_WIFI_RF_KILL_N */
  74         PCH_GPIO_OUT_HIGH,      /* 52: TOUCH_PNL_RST_N_R */
  75         PCH_GPIO_INPUT,         /* 53: SNSR_HUB_I2C_WAKE / ALS_INT_MCP */
  76         PCH_GPIO_ACPI_SCI,      /* 54: NGFF_SLTB_SSD_MC_WAKE_N */
  77         PCH_GPIO_IRQ_EDGE,      /* 55: TOUCHPAD_INTR_N */
  78         PCH_GPIO_INPUT,         /* 56: NGFF_SLTB_WWAN_SSD_DET1 */
  79         PCH_GPIO_OUT_HIGH,      /* 57: NGFF_SLTB_WWAN_PWREN */
  80         PCH_GPIO_OUT_LOW,       /* 58: SLATEMODE_HALLOUT_R */
  81         PCH_GPIO_OUT_HIGH,      /* 59: USB2_CAM_PWREN */
  82         PCH_GPIO_OUT_LOW,       /* 60: USB_CR_PWREN_N */
  83         PCH_GPIO_NATIVE,        /* 61: PM_SUS_STAT_N */
  84         PCH_GPIO_NATIVE,        /* 62: SUS_CK */
  85         PCH_GPIO_NATIVE,        /* 63: SLP_S5_R_N */
  86         PCH_GPIO_NATIVE,        /* 64: LPSS_SDIO_CLK_CMNHDR_R */
  87         PCH_GPIO_NATIVE,        /* 65: LPSS_SDIO_CMD_CMNHDR_R */
  88         PCH_GPIO_NATIVE,        /* 66: LPSS_SDIO_D0_CMNHDR_R */
  89         PCH_GPIO_NATIVE,        /* 67: LPSS_SDIO_D1_CMNHDR_R */
  90         PCH_GPIO_NATIVE,        /* 68: LPSS_SDIO_D2_CMNHDR_R */
  91         PCH_GPIO_NATIVE,        /* 69: LPSS_SDIO_D3_CMNHDR_R1 */
  92         PCH_GPIO_NATIVE,        /* 70: NGFF_SLTA_WIFI_PWREN_N_R */
  93         PCH_GPIO_OUT_HIGH,      /* 71: MPHY_PWREN */
  94         PCH_GPIO_NATIVE,        /* 72: PM_BATLOW_R_N */
  95         PCH_GPIO_NATIVE,        /* 73: PCH_NOT_N */
  96         PCH_GPIO_NATIVE,        /* 74: SML1_DATA */
  97         PCH_GPIO_NATIVE,        /* 75: SML1_CK */
  98         PCH_GPIO_OUT_HIGH,      /* 76: PCH_AUDIO_PWR_R */
  99         PCH_GPIO_OUT_LOW,       /* 77: PC_SLTB_SSD_RST_N_R */
 100         PCH_GPIO_INPUT,         /* 78: PM_EXTTS0_EC_N */
 101         PCH_GPIO_IRQ_EDGE,      /* 79: SIO1007_IRQ_N */
 102         PCH_GPIO_INPUT,         /* 80: PM_EXTTS1_R_N */
 103         PCH_GPIO_NATIVE,        /* 81: PCH_HDA_SPKR */
 104         PCH_GPIO_NATIVE,        /* 82: H_RCIN_N */
 105         PCH_GPIO_NATIVE,        /* 83: LPSS_GSPI0_CS_R_N */
 106         PCH_GPIO_NATIVE,        /* 84: LPSS_GSPI0_CLK_R */
 107         PCH_GPIO_NATIVE,        /* 85: LPSS_GSPI0_MISO_R */
 108         PCH_GPIO_NATIVE,        /* 86: LPSS_GSPI0_MOSI_BBS0_R */
 109         PCH_GPIO_NATIVE,        /* 87: LPSS_GSPI1_CS_R_N */
 110         PCH_GPIO_NATIVE,        /* 88: LPSS_GSPI1_CLK_R */
 111         PCH_GPIO_NATIVE,        /* 89: LPSS_GSPI1_MISO_R */
 112         PCH_GPIO_OUT_LOW,       /* 90: NGFF_SLTA_WIFI_RST_N */
 113         PCH_GPIO_NATIVE,        /* 91: LPSS_UART0_RXD */
 114         PCH_GPIO_NATIVE,        /* 92: LPSS_UART0_TXD */
 115         PCH_GPIO_NATIVE,        /* 93: LPSS_UART0_RTS_N */
 116         PCH_GPIO_NATIVE,        /* 94: LPSS_UART0_CTS_N */
 117         PCH_GPIO_END
 118 };
 119
 120 #endif