src/mainboard/intel/strago/ramstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2014 Intel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <soc/ramstage.h>
  17 #include <boardid.h>
  18 #include "onboard.h"
  19
  20 void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
  21 {
  22         if (board_id() == BOARD_BCRD2) {
  23                         params->ChvSvidConfig = SVID_PMIC_CONFIG;
  24                         params->PMIC_I2CBus = BCRD2_PMIC_I2C_BUS;
  25         }
  26 }