src/mainboard/intel/strago/cmos.layout

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007-2008 coresystems GmbH
   5 ## Copyright (C) 2015 Intel Corp.
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; version 2 of the License.
  10 ##
  11 ## This program is distributed in the hope that it will be useful,
  12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ## GNU General Public License for more details.
  15 ##
  16
  17 # -----------------------------------------------------------------
  18 entries
  19
  20 #start-bit length  config config-ID    name
  21 #0            8       r       0        seconds
  22 #8            8       r       0        alarm_seconds
  23 #16           8       r       0        minutes
  24 #24           8       r       0        alarm_minutes
  25 #32           8       r       0        hours
  26 #40           8       r       0        alarm_hours
  27 #48           8       r       0        day_of_week
  28 #56           8       r       0        day_of_month
  29 #64           8       r       0        month
  30 #72           8       r       0        year
  31 # -----------------------------------------------------------------
  32 # Status Register A
  33 #80           4       r       0        rate_select
  34 #84           3       r       0        REF_Clock
  35 #87           1       r       0        UIP
  36 # -----------------------------------------------------------------
  37 # Status Register B
  38 #88           1       r       0        auto_switch_DST
  39 #89           1       r       0        24_hour_mode
  40 #90           1       r       0        binary_values_enable
  41 #91           1       r       0        square-wave_out_enable
  42 #92           1       r       0        update_finished_enable
  43 #93           1       r       0        alarm_interrupt_enable
  44 #94           1       r       0        periodic_interrupt_enable
  45 #95           1       r       0        disable_clock_updates
  46 # -----------------------------------------------------------------
  47 # Status Register C
  48 #96           4       r       0        status_c_rsvd
  49 #100          1       r       0        uf_flag
  50 #101          1       r       0        af_flag
  51 #102          1       r       0        pf_flag
  52 #103          1       r       0        irqf_flag
  53 # -----------------------------------------------------------------
  54 # Status Register D
  55 #104          7       r       0        status_d_rsvd
  56 #111          1       r       0        valid_cmos_ram
  57 # -----------------------------------------------------------------
  58 # Diagnostic Status Register
  59 #112          8       r       0        diag_rsvd1
  60
  61 # -----------------------------------------------------------------
  62 0          120       r       0        reserved_memory
  63 #120        264       r       0        unused
  64
  65 # -----------------------------------------------------------------
  66 # RTC_BOOT_BYTE (coreboot hardcoded)
  67 384          1       e       4        boot_option
  68 385          1       e       4        last_boot
  69 388          4       r       0        reboot_bits
  70 #390          2       r       0        unused?
  71
  72 # -----------------------------------------------------------------
  73 # coreboot config options: console
  74 392          3       e       5        baud_rate
  75 395          4       e       6        debug_level
  76 #399          1       r       0        unused
  77
  78 # coreboot config options: cpu
  79 400          1       e       2        hyper_threading
  80 #401          7       r       0        unused
  81
  82 # coreboot config options: southbridge
  83 408          1       e       1        nmi
  84 409          2       e       7        power_on_after_fail
  85 #411          5       r       0        unused
  86
  87 # coreboot config options: bootloader
  88 #Used by ChromeOS:
  89 416        128       r        0        vbnv
  90 #544        440       r       0        unused
  91
  92 # SandyBridge MRC Scrambler Seed values
  93 896         32        r       0        mrc_scrambler_seed
  94 928         32        r       0        mrc_scrambler_seed_s3
  95
  96 # coreboot config options: check sums
  97 984         16       h       0        check_sum
  98 #1000        24       r       0        amd_reserved
  99
 100 # -----------------------------------------------------------------
 101
 102 enumerations
 103
 104 #ID value   text
 105 1     0     Disable
 106 1     1     Enable
 107 2     0     Enable
 108 2     1     Disable
 109 4     0     Fallback
 110 4     1     Normal
 111 5     0     115200
 112 5     1     57600
 113 5     2     38400
 114 5     3     19200
 115 5     4     9600
 116 5     5     4800
 117 5     6     2400
 118 5     7     1200
 119 6     1     Emergency
 120 6     2     Alert
 121 6     3     Critical
 122 6     4     Error
 123 6     5     Warning
 124 6     6     Notice
 125 6     7     Info
 126 6     8     Debug
 127 6     9     Spew
 128 7     0     Disable
 129 7     1     Enable
 130 7     2     Keep
 131 # -----------------------------------------------------------------
 132 checksums
 133
 134 checksum 392 415 984
 135
 136