src/mainboard/intel/d810e2cb/gpio.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #define PME_DEV                 PNP_DEV(0x4e, 0x0a)
  18 #define PME_IO_BASE_ADDR        0x800      /* Runtime register base address */
  19
  20 /* Early mainboard specific GPIO setup. */
  21 static void mb_gpio_init(void)
  22 {
  23         device_t dev;
  24         uint16_t port;
  25
  26         /* Southbridge GPIOs. */
  27         /* Set the LPC device statically. */
  28         dev = PCI_DEV(0x0, 0x1f, 0x0);
  29
  30         /* Set the value for GPIO base address register and enable GPIO. */
  31         pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
  32         pci_write_config8(dev, GPIO_CNTL, 0x10);
  33
  34         udelay(10);
  35         outl(0x1a203180, GPIO_BASE_ADDR + 0x00); /* GPIO_USE_SEL */
  36         outl(0x0000ffff, GPIO_BASE_ADDR + 0x04); /* GP_IO_SEL */
  37         outl(0x13bf0000, GPIO_BASE_ADDR + 0x0c); /* GP_LVL */
  38         outl(0x00040000, GPIO_BASE_ADDR + 0x18); /* GPO_BLINK */
  39         outl(0x000039ff, GPIO_BASE_ADDR + 0x2c); /* GPI_INV */
  40
  41         /* Super I/O GPIOs. */
  42         dev = PME_DEV;
  43         port = dev >> 8;
  44
  45         /* Enter the configuration state. */
  46         outb(0x55, port);
  47         pnp_set_logical_device(dev);
  48         pnp_set_enable(dev, 0);
  49         pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
  50         pnp_set_enable(dev, 1);
  51
  52         /* GP10 - J1B1 */
  53         outl(0x01, PME_IO_BASE_ADDR + 0x23);
  54
  55         /* GP11 - J1B2 */
  56         outl(0x01, PME_IO_BASE_ADDR + 0x24);
  57
  58         /* GP12 - J2B1 */
  59         outl(0x01, PME_IO_BASE_ADDR + 0x25);
  60
  61         /* GP13 - J2B2 */
  62         outl(0x01, PME_IO_BASE_ADDR + 0x26);
  63
  64         /* GP14 - J1X */
  65         outl(0x01, PME_IO_BASE_ADDR + 0x27);
  66
  67         /* GP15 - J1Y */
  68         outl(0x01, PME_IO_BASE_ADDR + 0x28);
  69
  70         /* GP16 - J2X */
  71         outl(0x01, PME_IO_BASE_ADDR + 0x29);
  72
  73         /* GP17 - J2Y */
  74         outl(0x01, PME_IO_BASE_ADDR + 0x2a);
  75
  76         /* GP20 - 8042 P17 */
  77         outl(0x01, PME_IO_BASE_ADDR + 0x2b);
  78
  79         /* GP21 - 8042 P16 */
  80         outl(0x00, PME_IO_BASE_ADDR + 0x2c);
  81
  82         /* GP22 - 8042 P12 */
  83         outl(0x00, PME_IO_BASE_ADDR + 0x2d);
  84
  85         /* GP24 */
  86         outl(0x00, PME_IO_BASE_ADDR + 0x2f);
  87
  88         /* GP25 - MIDI_IN */
  89         outl(0x01, PME_IO_BASE_ADDR + 0x30);
  90
  91         /* GP26 - MIDI_OUT */
  92         outl(0x01, PME_IO_BASE_ADDR + 0x31);
  93
  94         /* GP27 - nIO_SMI */
  95         outl(0x04, PME_IO_BASE_ADDR + 0x32);
  96
  97         /* GP30 - FAN_TACH2 */
  98         outl(0x05, PME_IO_BASE_ADDR + 0x33);
  99
 100         /* GP31 - FAN_TACH1 */
 101         outl(0x05, PME_IO_BASE_ADDR + 0x34);
 102
 103         /* GP32 - FAN2 */
 104         outl(0x04, PME_IO_BASE_ADDR + 0x35);
 105
 106         /* GP33 - FAN1 */
 107         outl(0x04, PME_IO_BASE_ADDR + 0x36);
 108
 109         /* GP34 - IRRX2 */
 110         outl(0x05, PME_IO_BASE_ADDR + 0x37);
 111
 112         /* GP35 - IRTX2 */
 113         outl(0x04, PME_IO_BASE_ADDR + 0x38);
 114
 115         /* GP36 - nKBDRST */
 116         outl(0x84, PME_IO_BASE_ADDR + 0x39);
 117
 118         /* GP37 - A20M */
 119         outl(0x84, PME_IO_BASE_ADDR + 0x3a);
 120
 121         /* GP40 - DRVDEN0 */
 122         outl(0x04, PME_IO_BASE_ADDR + 0x3b);
 123
 124         /* GP41 - DRVDEN1 */
 125         outl(0x04, PME_IO_BASE_ADDR + 0x3c);
 126
 127         /* GP42 - nIO_PME */
 128         outl(0x84, PME_IO_BASE_ADDR + 0x3d);
 129
 130         /* GP43 */
 131         outl(0x00, PME_IO_BASE_ADDR + 0x3e);
 132
 133         /* GP50 - nIR2 */
 134         outl(0x05, PME_IO_BASE_ADDR + 0x3f);
 135
 136         /* GP51 - nDCD2 */
 137         outl(0x05, PME_IO_BASE_ADDR + 0x40);
 138
 139         /* GP52 - RXD2 */
 140         outl(0x05, PME_IO_BASE_ADDR + 0x41);
 141
 142         /* GP53 - TXD2 */
 143         outl(0x04, PME_IO_BASE_ADDR + 0x42);
 144
 145         /* GP54 - nDSR2 */
 146         outl(0x05, PME_IO_BASE_ADDR + 0x43);
 147
 148         /* GP55 - nRTS2 */
 149         outl(0x04, PME_IO_BASE_ADDR + 0x44);
 150
 151         /* GP56 - nCTS2 */
 152         outl(0x05, PME_IO_BASE_ADDR + 0x45);
 153
 154         /* GP57 - nDTR2 */
 155         outl(0x04, PME_IO_BASE_ADDR + 0x46);
 156
 157         /* GP60 - LED1 */
 158         outl(0x84, PME_IO_BASE_ADDR + 0x47);
 159
 160         /* GP61 - LED2 */
 161         outl(0x84, PME_IO_BASE_ADDR + 0x48);
 162
 163         /* GP1 */
 164         outl(0x00, PME_IO_BASE_ADDR + 0x4b);
 165
 166         /* GP2 */
 167         outl(0x14, PME_IO_BASE_ADDR + 0x4c);
 168
 169         /* GP3 */
 170         outl(0xda, PME_IO_BASE_ADDR + 0x4d);
 171
 172         /* GP4 */
 173         outl(0x08, PME_IO_BASE_ADDR + 0x4e);
 174
 175         /* GP5 */
 176         outl(0x00, PME_IO_BASE_ADDR + 0x4f);
 177
 178         /* GP6 */
 179         outl(0x00, PME_IO_BASE_ADDR + 0x50);
 180
 181         /* FAN1 */
 182         outl(0x01, PME_IO_BASE_ADDR + 0x56);
 183
 184         /* FAN2 */
 185         outl(0x01, PME_IO_BASE_ADDR + 0x57);
 186
 187         /* Fan Control */
 188         outl(0xf0, PME_IO_BASE_ADDR + 0x58);
 189
 190         /* Fan1 Preload */
 191         outl(0x00, PME_IO_BASE_ADDR + 0x5b);
 192
 193         /* Fan2 Preload */
 194         outl(0x00, PME_IO_BASE_ADDR + 0x5c);
 195
 196         /* LED1 */
 197         outl(0x03, PME_IO_BASE_ADDR + 0x5d);
 198
 199         /* LED2 */
 200         outl(0x03, PME_IO_BASE_ADDR + 0x5e);
 201
 202         /* Keyboard Scan Code */
 203         outl(0x00, PME_IO_BASE_ADDR + 0x5f);
 204
 205         /* Exit the configuration state. */
 206         outb(0xaa, port);
 207 }