2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
16 if BOARD_INTEL_BAYLEYBAY_FSP
18 config BOARD_SPECIFIC_OPTIONS # dummy
20 select SOC_INTEL_FSP_BAYTRAIL
21 select BOARD_ROMSIZE_KB_2048
22 select HAVE_ACPI_TABLES
23 select HAVE_OPTION_TABLE
24 select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT
25 select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
26 select TSC_MONOTONIC_TIMER
30 default "intel/bayleybay_fsp"
32 config MAINBOARD_PART_NUMBER
34 default "Bayley Bay CRB (FSP)"
40 config CACHE_ROM_SIZE_OVERRIDE
46 default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
52 config ENABLE_FSP_FAST_BOOT
54 depends on HAVE_FSP_BIN
57 config VIRTUAL_ROM_SIZE
59 depends on ENABLE_FSP_FAST_BOOT
62 config FSP_PACKAGE_DEFAULT
63 bool "Configure defaults for the Intel FSP package"
68 default y if FSP_PACKAGE_DEFAULT
70 endif # BOARD_INTEL_BAYLEYBAY_FSP