src/mainboard/intel/baskingridge/chromeos.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <string.h>
  17 #include <bootmode.h>
  18 #include <arch/io.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <southbridge/intel/lynxpoint/pch.h>
  22 #include <southbridge/intel/lynxpoint/gpio.h>
  23
  24 #ifndef __PRE_RAM__
  25 #include <boot/coreboot_tables.h>
  26
  27 #define GPIO_COUNT      6
  28
  29 void fill_lb_gpios(struct lb_gpios *gpios)
  30 {
  31         device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
  32         u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
  33
  34         if (!gpio_base)
  35                 return;
  36
  37         u32 gp_lvl  = inl(gpio_base + GP_LVL);
  38         u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
  39         u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
  40
  41         gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
  42         gpios->count = GPIO_COUNT;
  43
  44         /* Write Protect: GPIO22 */
  45         gpios->gpios[0].port = 0;
  46         gpios->gpios[0].polarity = ACTIVE_LOW;
  47         gpios->gpios[0].value = (gp_lvl >> 22) & 1;
  48         strncpy((char *)gpios->gpios[0].name,"write protect",
  49                                                         GPIO_MAX_NAME_LENGTH);
  50
  51         /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */
  52         gpios->gpios[1].port = 69;
  53         gpios->gpios[1].polarity = ACTIVE_HIGH;
  54         gpios->gpios[1].value = (gp_lvl3 >> (69-64)) & 1;
  55         strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
  56
  57         /* Developer: GPIO48 - BIOS_RESP - J8E4 (silkscreen: J8E3) */
  58         gpios->gpios[2].port = 48;
  59         gpios->gpios[2].polarity = ACTIVE_LOW;
  60         gpios->gpios[2].value = (gp_lvl2 >> (48-32)) & 1;
  61         strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
  62
  63         /* Hard code the lid switch GPIO to open. */
  64         gpios->gpios[3].port = -1;
  65         gpios->gpios[3].polarity = ACTIVE_HIGH;
  66         gpios->gpios[3].value = 1;
  67         strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
  68
  69         /* Power Button */
  70         gpios->gpios[4].port = -1;
  71         gpios->gpios[4].polarity = ACTIVE_HIGH;
  72         gpios->gpios[4].value = 0;
  73         strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
  74
  75         /* Did we load the VGA option ROM? */
  76         gpios->gpios[5].port = -1;
  77         gpios->gpios[5].polarity = ACTIVE_HIGH;
  78         gpios->gpios[5].value = gfx_get_init_done();
  79         strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
  80 }
  81 #endif
  82
  83 int get_developer_mode_switch(void)
  84 {
  85         device_t dev;
  86 #ifdef __PRE_RAM__
  87         dev = PCI_DEV(0, 0x1f, 0);
  88 #else
  89         dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
  90 #endif
  91         u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
  92         u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
  93
  94         /*
  95          * Developer: GPIO48, Connected to J8E4, however the silkscreen says
  96          * J8E3. The jumper is active low.
  97          */
  98         return !((gp_lvl2 >> (48-32)) & 1);
  99 }
 100
 101 int get_recovery_mode_switch(void)
 102 {
 103         device_t dev;
 104 #ifdef __PRE_RAM__
 105         dev = PCI_DEV(0, 0x1f, 0);
 106 #else
 107         dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
 108 #endif
 109         u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
 110         u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
 111
 112         /*
 113          * Recovery: GPIO69, Connected to J8E3, however the silkscreen says
 114          * J8E2. The jump is active high.
 115          */
 116         return (gp_lvl3 >> (69-64)) & 1;
 117 }
 118
 119 int get_write_protect_state(void)
 120 {
 121         return 0;
 122 }