2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
20 Name(_ADR, 0x00140001)
27 /* Some timing tables */
28 Name(UDTT, Package(){ /* Udma timing table */
29 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */
32 Name(MDTT, Package(){ /* MWDma timing table */
33 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */
36 Name(POTT, Package(){ /* Pio timing table */
37 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */
40 /* Some timing register value tables */
41 Name(MDRT, Package(){ /* MWDma timing register table */
42 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */
46 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */
49 OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
50 Field(ICRG, AnyAcc, NoLock, Preserve)
52 PPTS, 8, /* Primary PIO Slave Timing */
53 PPTM, 8, /* Primary PIO Master Timing */
54 OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */
55 PMTM, 8, /* Primary MWDMA Master Timing */
56 OFFSET(0x08), PPCR, 8, /* Primary PIO Control */
57 OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */
58 PPSM, 4, /* Primary PIO slave Mode */
59 OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */
60 OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */
61 PDSM, 4, /* Primary UltraDMA Mode */
64 Method(GTTM, 1) /* get total time*/
66 Store(And(Arg0, 0x0F), Local0) /* Recovery Width */
68 Store(ShiftRight(Arg0, 4), Local1) /* Command Width */
70 Return(Multiply(30, Add(Local0, Local1)))
78 NAME(OTBF, Buffer(20) { /* out buffer */
79 0xFF, 0xFF, 0xFF, 0xFF,
80 0xFF, 0xFF, 0xFF, 0xFF,
81 0xFF, 0xFF, 0xFF, 0xFF,
82 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
85 CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */
86 CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */
87 CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */
88 CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
89 CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
91 /* Just return if the channel is disabled */
92 If(And(PPCR, 0x01)) { /* primary PIO control */
96 /* Always tell them independent timing available and IOChannelReady used on both drives */
99 Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */
100 Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */
102 If(And(PDCR, 0x01)) { /* It's under UDMA mode */
104 Store(DerefOf(Index(UDTT, PDMM)), DSD0)
107 Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */
110 If(And(PDCR, 0x02)) { /* It's under UDMA mode */
112 Store(DerefOf(Index(UDTT, PDSM)), DSD1)
115 Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */
118 Return(OTBF) /* out buffer */
119 } /* End Method(_GTM) */
121 Method(_STM, 3, NotSerialized)
123 NAME(INBF, Buffer(20) { /* in buffer */
124 0xFF, 0xFF, 0xFF, 0xFF,
125 0xFF, 0xFF, 0xFF, 0xFF,
126 0xFF, 0xFF, 0xFF, 0xFF,
127 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
130 CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */
131 CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */
132 CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */
133 CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
134 CreateDwordField(INBF, 16, BFFG) /*buffer flag */
136 Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
137 Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
138 Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
139 Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
141 Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
142 Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
144 If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */
145 Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
146 Divide(Local0, 7, PDMM,)
150 If(LNotEqual(DSD0, 0xFFFFFFFF)) {
151 Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
152 Store(DerefOf(Index(MDRT, Local0)), PMTM)
156 If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */
157 Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
158 Divide(Local0, 7, PDSM,)
162 If(LNotEqual(DSD1, 0xFFFFFFFF)) {
163 Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
164 Store(DerefOf(Index(MDRT, Local0)), PMTS)
168 } /*End Method(_STM) */
173 Name(CMBF, Buffer(21) {
174 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
175 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
176 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
178 CreateByteField(CMBF, 1, POMD)
179 CreateByteField(CMBF, 8, DMMD)
180 CreateByteField(CMBF, 5, CMDA)
181 CreateByteField(CMBF, 12, CMDB)
182 CreateByteField(CMBF, 19, CMDC)
190 If(And(PDCR, 0x01)) {
195 (MDTT, MLE, GTTM(PMTM),
197 If(LLess(Local0, 3)) {
198 Or(0x20, Local0, DMMD)
203 } /* End Device(MST) */
209 Name(CMBF, Buffer(21) {
210 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
211 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
212 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
214 CreateByteField(CMBF, 1, POMD)
215 CreateByteField(CMBF, 8, DMMD)
216 CreateByteField(CMBF, 5, CMDA)
217 CreateByteField(CMBF, 12, CMDB)
218 CreateByteField(CMBF, 19, CMDC)
226 If(And(PDCR, 0x02)) {
231 (MDTT, MLE, GTTM(PMTS),
233 If(LLess(Local0, 3)) {
234 Or(0x20, Local0, DMMD)
239 } /* End Device(SLAV) */