src/mainboard/google/veyron_danger/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2014 Rockchip Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <arch/cache.h>
  17 #include <arch/exception.h>
  18 #include <arch/io.h>
  19 #include <arch/stages.h>
  20 #include <armv7.h>
  21 #include <assert.h>
  22 #include <cbfs.h>
  23 #include <cbmem.h>
  24 #include <console/console.h>
  25 #include <delay.h>
  26 #include <program_loading.h>
  27 #include <soc/sdram.h>
  28 #include <soc/clock.h>
  29 #include <soc/pwm.h>
  30 #include <soc/grf.h>
  31 #include <soc/rk808.h>
  32 #include <soc/tsadc.h>
  33 #include <stdlib.h>
  34 #include <symbols.h>
  35 #include <timestamp.h>
  36 #include <types.h>
  37 #include <vendorcode/google/chromeos/chromeos.h>
  38
  39 #include "board.h"
  40
  41 static void regulate_vdd_log(unsigned int mv)
  42 {
  43         unsigned int duty_ns;
  44         const u32 period_ns = 2000;     /* pwm period: 2000ns */
  45         const u32 max_regulator_mv = 1350;      /* 1.35V */
  46         const u32 min_regulator_mv = 870;       /* 0.87V */
  47
  48         write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
  49
  50         assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
  51
  52         duty_ns = (max_regulator_mv - mv) * period_ns /
  53                         (max_regulator_mv - min_regulator_mv);
  54
  55         pwm_init(1, period_ns, duty_ns);
  56 }
  57
  58 static void configure_l2ctlr(void)
  59 {
  60         uint32_t l2ctlr;
  61
  62         l2ctlr = read_l2ctlr();
  63         l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
  64
  65         /*
  66         * Data RAM write latency: 2 cycles
  67         * Data RAM read latency: 2 cycles
  68         * Data RAM setup latency: 1 cycle
  69         * Tag RAM write latency: 1 cycle
  70         * Tag RAM read latency: 1 cycle
  71         * Tag RAM setup latency: 1 cycle
  72         */
  73         l2ctlr |= (1 << 3 | 1 << 0);
  74         write_l2ctlr(l2ctlr);
  75 }
  76
  77 void main(void)
  78 {
  79         timestamp_add_now(TS_START_ROMSTAGE);
  80
  81         console_init();
  82         configure_l2ctlr();
  83         tsadc_init();
  84
  85         /* Need to power cycle SD card to ensure it is properly reset. */
  86         sdmmc_power_off();
  87
  88         /* vdd_log 1200mv is enough for ddr run 666Mhz */
  89         regulate_vdd_log(1200);
  90
  91         timestamp_add_now(TS_BEFORE_INITRAM);
  92
  93         sdram_init(get_sdram_config());
  94
  95         timestamp_add_now(TS_AFTER_INITRAM);
  96
  97         /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
  98         mmu_config_range((uintptr_t)_dram/MiB,
  99                          sdram_size_mb(), DCACHE_WRITEBACK);
 100         mmu_config_range((uintptr_t)_dma_coherent/MiB,
 101                          _dma_coherent_size/MiB, DCACHE_OFF);
 102
 103         cbmem_initialize_empty();
 104
 105         run_ramstage();
 106 }