2 ## This file is part of the coreboot project.
4 ## Copyright 2014 Rockchip Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
16 if BOARD_GOOGLE_VEYRON_BRAIN
18 config BOARD_SPECIFIC_OPTIONS # dummy
21 select BOARD_ROMSIZE_KB_4096
22 select COMMON_CBFS_SPI_WRAPPER
23 select HAVE_HARD_RESET
24 select MAINBOARD_HAS_NATIVE_VGA_INIT
25 select MAINBOARD_DO_NATIVE_VGA_INIT
26 select MAINBOARD_HAS_CHROMEOS
27 select RAM_CODE_SUPPORT
28 select SOC_ROCKCHIP_RK3288
30 select SPI_FLASH_GIGADEVICE
31 select SPI_FLASH_WINBOND
34 select CHROMEOS_VBNV_FLASH
35 select PHYSICAL_REC_SWITCH
36 select VIRTUAL_DEV_SWITCH
40 default google/veyron_brain
42 config MAINBOARD_PART_NUMBER
44 default "Veyron_Brain"
46 config MAINBOARD_VENDOR
50 config BOOT_MEDIA_SPI_BUS
54 config DRIVER_TPM_I2C_BUS
58 config DRIVER_TPM_I2C_ADDR
62 config CONSOLE_SERIAL_UART_ADDRESS
64 depends on DRIVERS_UART
71 endif # BOARD_GOOGLE_VEYRON_BRAIN