src/mainboard/google/stout/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2010 coresystems GmbH
   5  * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <stdint.h>
  18 #include <string.h>
  19 #include <lib.h>
  20 #include <timestamp.h>
  21 #include <arch/io.h>
  22 #include <device/pci_def.h>
  23 #include <device/pnp_def.h>
  24 #include <cpu/x86/lapic.h>
  25 #include <pc80/mc146818rtc.h>
  26 #include <arch/acpi.h>
  27 #include <cbmem.h>
  28 #include <console/console.h>
  29 #include <northbridge/intel/sandybridge/sandybridge.h>
  30 #include <northbridge/intel/sandybridge/raminit.h>
  31 #include <southbridge/intel/bd82x6x/pch.h>
  32 #include <southbridge/intel/bd82x6x/gpio.h>
  33 #include <arch/cpu.h>
  34 #include <cpu/x86/bist.h>
  35 #include <cpu/x86/msr.h>
  36 #include <halt.h>
  37 #include "gpio.h"
  38 #include <bootmode.h>
  39 #include <tpm.h>
  40 #include <cbfs.h>
  41 #include <ec/quanta/it8518/ec.h>
  42 #include "ec.h"
  43 #include "onboard.h"
  44
  45 static void pch_enable_lpc(void)
  46 {
  47         /*
  48          * Enable:
  49          *  EC Decode Range Port62/66
  50          *  SuperIO Port2E/2F
  51          *  PS/2 Keyboard/Mouse Port60/64
  52          *  FDD Port3F0h-3F5h and Port3F7h
  53          */
  54         pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
  55                         CNF1_LPC_EN | FDD_LPC_EN);
  56
  57         /* Stout EC Decode Range Port68/6C */
  58         pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001));
  59 }
  60
  61 static void rcba_config(void)
  62 {
  63         u32 reg32;
  64
  65         /*
  66          *             GFX         INTA -> PIRQA (MSI)
  67          * D20IP_XHCI  XHCI        INTA -> PIRQD (MSI)
  68          * D26IP_E2P   EHCI #2     INTA -> PIRQF
  69          * D27IP_ZIP   HDA         INTA -> PIRQA (MSI)
  70          * D28IP_P2IP  WLAN        INTA -> PIRQD
  71          * D28IP_P3IP  Card Reader INTB -> PIRQE
  72          * D28IP_P6IP  LAN         INTC -> PIRQB
  73          * D29IP_E1P   EHCI #1     INTA -> PIRQD
  74          * D31IP_SIP   SATA        INTA -> PIRQB (MSI)
  75          * D31IP_SMIP  SMBUS       INTB -> PIRQH
  76          */
  77
  78         /* Device interrupt pin register (board specific) */
  79         RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
  80                 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
  81         RCBA32(D30IP) = (NOINT << D30IP_PIP);
  82         RCBA32(D29IP) = (INTA << D29IP_E1P);
  83         RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
  84                 (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
  85                 (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) |
  86                 (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
  87         RCBA32(D27IP) = (INTA << D27IP_ZIP);
  88         RCBA32(D26IP) = (INTA << D26IP_E2P);
  89         RCBA32(D25IP) = (NOINT << D25IP_LIP);
  90         RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
  91         RCBA32(D20IP) = (INTA << D20IP_XHCIIP);
  92
  93         /* Device interrupt route registers */
  94         DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
  95         DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
  96         DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC);
  97         DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD);
  98         DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD);
  99         DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
 100         DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
 101         DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);
 102
 103         /* Enable IOAPIC (generic) */
 104         RCBA16(OIC) = 0x0100;
 105         /* PCH BWG says to read back the IOAPIC enable register */
 106         (void) RCBA16(OIC);
 107
 108         /* Disable unused devices (board specific) */
 109         reg32 = RCBA32(FD);
 110         reg32 |= PCH_DISABLE_ALWAYS;
 111         /* Disable PCI bridge so MRC does not probe this bus */
 112         reg32 |= PCH_DISABLE_P2P;
 113         RCBA32(FD) = reg32;
 114 }
 115
 116 // FIXME, this function is generic code that should go to sb/... or
 117 // nb/../early_init.c
 118 static void early_pch_init(void)
 119 {
 120         // Nothing to do for stout
 121 }
 122
 123         /*
 124          * The Stout EC needs to be reset to RW mode. It is important that
 125          * the RTC_PWR_STS is not set until ramstage EC init.
 126          */
 127 static void early_ec_init(void)
 128 {
 129         u8 ec_status = ec_read(EC_STATUS_REG);
 130         int rec_mode = IS_ENABLED(CONFIG_BOOTMODE_STRAPS) &&
 131                 get_recovery_mode_switch();
 132
 133         if (((ec_status & 0x3) == EC_IN_RO_MODE) ||
 134             ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)) {
 135
 136                 printk(BIOS_DEBUG, "EC Cold Boot Detected\n");
 137                 if (!rec_mode) {
 138                         /*
 139                          * Tell EC to exit RO mode
 140                          */
 141                         printk(BIOS_DEBUG, "EC will exit RO mode and boot normally\n");
 142                         ec_write_cmd(EC_CMD_EXIT_BOOT_BLOCK);
 143                         die("wait for ec to reset");
 144                 }
 145         } else {
 146                 printk(BIOS_DEBUG, "EC Warm Boot Detected\n");
 147                 ec_write_cmd(EC_CMD_WARM_RESET);
 148         }
 149 }
 150
 151 #include <cpu/intel/romstage.h>
 152 void main(unsigned long bist)
 153 {
 154         int boot_mode = 0;
 155         int cbmem_was_initted;
 156
 157         struct pei_data pei_data = {
 158                 .pei_version = PEI_VERSION,
 159                 .mchbar = (uintptr_t)DEFAULT_MCHBAR,
 160                 .dmibar = (uintptr_t)DEFAULT_DMIBAR,
 161                 .epbar = DEFAULT_EPBAR,
 162                 .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
 163                 .smbusbar = SMBUS_IO_BASE,
 164                 .wdbbar = 0x4000000,
 165                 .wdbsize = 0x1000,
 166                 .hpet_address = CONFIG_HPET_ADDRESS,
 167                 .rcba = (uintptr_t)DEFAULT_RCBABASE,
 168                 .pmbase = DEFAULT_PMBASE,
 169                 .gpiobase = DEFAULT_GPIOBASE,
 170                 .thermalbase = 0xfed08000,
 171                 .system_type = 0, // 0 Mobile, 1 Desktop/Server
 172                 .tseg_size = CONFIG_SMM_TSEG_SIZE,
 173                 .spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
 174                 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
 175                 .ec_present = 1,
 176                 // 0 = leave channel enabled
 177                 // 1 = disable dimm 0 on channel
 178                 // 2 = disable dimm 1 on channel
 179                 // 3 = disable dimm 0+1 on channel
 180                 .dimm_channel0_disabled = 2,
 181                 .dimm_channel1_disabled = 2,
 182                 .max_ddr3_freq = 1600,
 183                 .usb_port_config = {
 184                         /* enabled   usb oc pin    length */
 185                         { 1, 0, 0x0040 }, /* P0: USB 3.0 1  (OC0) */
 186                         { 1, 0, 0x0040 }, /* P1: USB 3.0 2  (OC0) */
 187                         { 0, 1, 0x0000 }, /* P2: Empty */
 188                         { 1, 1, 0x0040 }, /* P3: Camera (no OC) */
 189                         { 1, 1, 0x0040 }, /* P4: WLAN   (no OC) */
 190                         { 1, 1, 0x0040 }, /* P5: WWAN   (no OC) */
 191                         { 0, 1, 0x0000 }, /* P6: Empty */
 192                         { 0, 1, 0x0000 }, /* P7: Empty */
 193                         { 0, 5, 0x0000 }, /* P8: Empty */
 194                         { 1, 4, 0x0040 }, /* P9: USB 2.0 (AUO4) (OC4) */
 195                         { 0, 5, 0x0000 }, /* P10: Empty */
 196                         { 0, 5, 0x0000 }, /* P11: Empty */
 197                         { 0, 5, 0x0000 }, /* P12: Empty */
 198                         { 1, 5, 0x0040 }, /* P13: Bluetooth (no OC) */
 199                 },
 200                 .usb3 = {
 201                         .mode = XHCI_MODE,
 202                         .hs_port_switch_mask = XHCI_PORTS,
 203                         .preboot_support = XHCI_PREBOOT,
 204                         .xhci_streams = XHCI_STREAMS,
 205                 },
 206         };
 207
 208         timestamp_init(get_initial_timestamp());
 209         timestamp_add_now(TS_START_ROMSTAGE);
 210
 211         if (bist == 0)
 212                 enable_lapic();
 213
 214         pch_enable_lpc();
 215
 216         /* Enable GPIOs */
 217         pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
 218         pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
 219         setup_pch_gpios(&stout_gpio_map);
 220
 221         /* Initialize console device(s) */
 222         console_init();
 223
 224         /* Halt if there was a built in self test failure */
 225         report_bist_failure(bist);
 226
 227         if (MCHBAR16(SSKPD) == 0xCAFE) {
 228                 printk(BIOS_DEBUG, "soft reset detected\n");
 229                 boot_mode = 1;
 230
 231                 /* System is not happy after keyboard reset... */
 232                 printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
 233                 outb(0x6, 0xcf9);
 234                 halt();
 235         }
 236
 237
 238         /* Perform some early chipset initialization required
 239          * before RAM initialization can work
 240          */
 241         sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
 242         printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
 243
 244         boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
 245
 246         /* Do ec reset as early as possible, but skip it on S3 resume */
 247         if (boot_mode < 2)
 248                 early_ec_init();
 249
 250         post_code(0x38);
 251         /* Enable SPD ROMs and DDR-III DRAM */
 252         enable_smbus();
 253
 254         /* Prepare USB controller early in S3 resume */
 255         if (boot_mode == 2)
 256                 enable_usb_bar();
 257
 258         post_code(0x39);
 259
 260         post_code(0x3a);
 261         pei_data.boot_mode = boot_mode;
 262         timestamp_add_now(TS_BEFORE_INITRAM);
 263         sdram_initialize(&pei_data);
 264
 265         timestamp_add_now(TS_AFTER_INITRAM);
 266         post_code(0x3b);
 267         /* Perform some initialization that must run before stage2 */
 268         early_pch_init();
 269         post_code(0x3c);
 270
 271         rcba_config();
 272         post_code(0x3d);
 273
 274         quick_ram_check();
 275         post_code(0x3e);
 276
 277         cbmem_was_initted = !cbmem_recovery(boot_mode==2);
 278         if (boot_mode!=2)
 279                 save_mrc_data(&pei_data);
 280
 281         if (boot_mode==2 && !cbmem_was_initted) {
 282                 /* Failed S3 resume, reset to come up cleanly */
 283                 outb(0x6, 0xcf9);
 284                 halt();
 285         }
 286         northbridge_romstage_finalize(boot_mode==2);
 287
 288         post_code(0x3f);
 289         if (CONFIG_LPC_TPM) {
 290                 init_tpm(boot_mode == 2);
 291         }
 292 }