src/mainboard/google/smaug/pmic.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2015 Google Inc.
   5  * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef __MAINBOARD_GOOGLE_FOSTER_PMIC_H__
  18 #define __MAINBOARD_GOOGLE_FOSTER_PMIC_H__
  19
  20 #define MAX77620_SD0_REG                0x16
  21 #define MAX77620_SD1_REG                0x17
  22 #define MAX77620_SD2_REG                0x18
  23 #define MAX77620_SD3_REG                0x19
  24 #define MAX77620_VDVSSD0_REG            0x1B
  25 #define MAX77620_CNFG2SD_REG            0x22
  26
  27 #define MAX77620_CNFG1_L0_REG           0x23
  28 #define MAX77620_CNFG2_L0_REG           0x24
  29 #define MAX77620_CNFG1_L1_REG           0x25
  30 #define MAX77620_CNFG2_L1_REG           0x26
  31 #define MAX77620_CNFG1_L2_REG           0x27
  32 #define MAX77620_CNFG2_L2_REG           0x28
  33 #define MAX77620_CNFG1_L3_REG           0x29
  34 #define MAX77620_CNFG2_L3_REG           0x2A
  35 #define MAX77620_CNFG1_L4_REG           0x2B
  36 #define MAX77620_CNFG2_L4_REG           0x2C
  37 #define MAX77620_CNFG1_L5_REG           0x2D
  38 #define MAX77620_CNFG2_L5_REG           0x2E
  39 #define MAX77620_CNFG1_L6_REG           0x2F
  40 #define MAX77620_CNFG2_L6_REG           0x30
  41 #define MAX77620_CNFG1_L7_REG           0x31
  42 #define MAX77620_CNFG2_L7_REG           0x32
  43 #define MAX77620_CNFG1_L8_REG           0x33
  44 #define MAX77620_CNFG2_L8_REG           0x34
  45 #define MAX77620_CNFG3_LDO_REG          0x35
  46
  47 #define MAX77620_GPIO0_REG              0x36
  48 #define MAX77620_GPIO1_REG              0x37
  49 #define MAX77620_GPIO2_REG              0x38
  50 #define MAX77620_GPIO3_REG              0x39
  51 #define MAX77620_GPIO4_REG              0x3A
  52 #define MAX77620_GPIO5_REG              0x3B
  53 #define MAX77620_GPIO6_REG              0x3C
  54 #define MAX77620_GPIO7_REG              0x3D
  55 #define MAX77620_GPIO_PUE_GPIO          0x3E
  56 #define MAX77620_GPIO_PDE_GPIO          0x3F
  57
  58 #define MAX77620_AME_GPIO               0x40
  59 #define MAX77620_REG_ONOFF_CFG1         0x41
  60 #define MAX77620_REG_ONOFF_CFG2         0x42
  61
  62 #define MAX77620_CID0_REG               0x58
  63 #define MAX77620_CID1_REG               0x59
  64 #define MAX77620_CID2_REG               0x5A
  65 #define MAX77620_CID3_REG               0x5B
  66 #define MAX77620_CID4_REG               0x5C
  67 #define MAX77620_CID5_REG               0x5D
  68
  69 #define MAX77621_VOUT_REG               0x00
  70 #define MAX77621_VOUT_DVC_REG           0x01
  71 #define MAX77621_CONTROL1_REG           0x02
  72 #define MAX77621_CONTROL2_REG           0x03
  73
  74 void pmic_init(unsigned bus);
  75 void pmic_write_reg_77620(unsigned bus, uint8_t reg, uint8_t val,
  76                                         int delay);
  77
  78 #endif /* __MAINBOARD_GOOGLE_FOSTER_PMIC_H__ */