src/mainboard/google/peppy/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2010 coresystems GmbH
   5  * Copyright (C) 2012 Google Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <delay.h>
  18 #include <stdint.h>
  19 #include <stdlib.h>
  20 #include <string.h>
  21 #include <cbfs.h>
  22 #include <console/console.h>
  23 #include <cpu/intel/haswell/haswell.h>
  24 #include "ec/google/chromeec/ec.h"
  25 #include <northbridge/intel/haswell/haswell.h>
  26 #include <northbridge/intel/haswell/raminit.h>
  27 #include <southbridge/intel/lynxpoint/pch.h>
  28 #include <southbridge/intel/lynxpoint/lp_gpio.h>
  29 #include "gpio.h"
  30 #include "onboard.h"
  31
  32 const struct rcba_config_instruction rcba_config[] = {
  33
  34         /*
  35          *             GFX    INTA -> PIRQA (MSI)
  36          * D28IP_P1IP  PCIE   INTA -> PIRQA
  37          * D29IP_E1P   EHCI   INTA -> PIRQD
  38          * D20IP_XHCI  XHCI   INTA -> PIRQC (MSI)
  39          * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
  40          * D31IP_SMIP  SMBUS  INTB -> PIRQG
  41          * D31IP_TTIP  THRT   INTC -> PIRQA
  42          * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
  43          */
  44
  45         /* Device interrupt pin register (board specific) */
  46         RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
  47                         (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
  48         RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)),
  49         RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
  50                         (INTB << D28IP_P4IP)),
  51         RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)),
  52         RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)),
  53         RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)),
  54         RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)),
  55
  56         /* Device interrupt route registers */
  57         RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */
  58         RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */
  59         RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */
  60         RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */
  61         RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */
  62         RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */
  63         RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */
  64         RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */
  65
  66         /* Disable unused devices (board specific) */
  67         RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
  68
  69         RCBA_END_CONFIG,
  70 };
  71
  72 /* Copy SPD data for on-board memory */
  73 static void copy_spd(struct pei_data *peid)
  74 {
  75         const int gpio_vector[] = {13, 9, 47, -1};
  76         int spd_index = get_gpios(gpio_vector);
  77         char *spd_file;
  78         size_t spd_file_len;
  79
  80         printk(BIOS_DEBUG, "SPD index %d\n", spd_index);
  81         spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
  82                                                 &spd_file_len);
  83         if (!spd_file)
  84                 die("SPD data not found.");
  85
  86         switch (google_chromeec_get_board_version()) {
  87         case PEPPY_BOARD_VERSION_PROTO:
  88                 /* Index 0 is 2GB config with CH0 only. */
  89                 if (spd_index == 0)
  90                         peid->dimm_channel1_disabled = 3;
  91                 break;
  92
  93         case PEPPY_BOARD_VERSION_EVT:
  94         default:
  95                 /* Index 0-2 are 4GB config with both CH0 and CH1.
  96                  * Index 4-6 are 2GB config with CH0 only. */
  97                 if (spd_index > 3)
  98                         peid->dimm_channel1_disabled = 3;
  99                 break;
 100         }
 101
 102         if (spd_file_len <
 103             ((spd_index + 1) * sizeof(peid->spd_data[0]))) {
 104                 printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
 105                 spd_index = 0;
 106         }
 107
 108         if (spd_file_len < sizeof(peid->spd_data[0]))
 109                 die("Missing SPD data.");
 110
 111         memcpy(peid->spd_data[0],
 112                spd_file +
 113                spd_index * sizeof(peid->spd_data[0]),
 114                sizeof(peid->spd_data[0]));
 115 }
 116
 117 void mainboard_romstage_entry(unsigned long bist)
 118 {
 119         struct pei_data pei_data = {
 120                 .pei_version = PEI_VERSION,
 121                 .mchbar = (uintptr_t)DEFAULT_MCHBAR,
 122                 .dmibar = (uintptr_t)DEFAULT_DMIBAR,
 123                 .epbar = DEFAULT_EPBAR,
 124                 .pciexbar = DEFAULT_PCIEXBAR,
 125                 .smbusbar = SMBUS_IO_BASE,
 126                 .wdbbar = 0x4000000,
 127                 .wdbsize = 0x1000,
 128                 .hpet_address = HPET_ADDR,
 129                 .rcba = (uintptr_t)DEFAULT_RCBA,
 130                 .pmbase = DEFAULT_PMBASE,
 131                 .gpiobase = DEFAULT_GPIOBASE,
 132                 .temp_mmio_base = 0xfed08000,
 133                 .system_type = 5, /* ULT */
 134                 .tseg_size = CONFIG_SMM_TSEG_SIZE,
 135                 .spd_addresses = { 0xff, 0x00, 0xff, 0x00 },
 136                 .ec_present = 1,
 137                 // 0 = leave channel enabled
 138                 // 1 = disable dimm 0 on channel
 139                 // 2 = disable dimm 1 on channel
 140                 // 3 = disable dimm 0+1 on channel
 141                 .dimm_channel0_disabled = 2,
 142                 .dimm_channel1_disabled = 2,
 143                 .max_ddr3_freq = 1600,
 144                 .usb_xhci_on_resume = 1,
 145                 .usb2_ports = {
 146                         /* Length, Enable, OCn#, Location */
 147                         { 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
 148                           USB_PORT_MINI_PCIE },
 149                         { 0x0040, 1, 0,               /* P1: Port A, CN10 */
 150                           USB_PORT_BACK_PANEL },
 151                         { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
 152                           USB_PORT_INTERNAL },
 153                         { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
 154                           USB_PORT_MINI_PCIE },
 155                         { 0x0040, 1, 2,               /* P4: Port B, CN6  */
 156                           USB_PORT_BACK_PANEL },
 157                         { 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */
 158                           USB_PORT_SKIP },
 159                         { 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
 160                           USB_PORT_FLEX },
 161                         { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
 162                           USB_PORT_SKIP },
 163                 },
 164                 .usb3_ports = {
 165                         /* Enable, OCn# */
 166                         { 1, 0               }, /* P1; Port A, CN6 */
 167                         { 0, USB_OC_PIN_SKIP }, /* P2; */
 168                         { 0, USB_OC_PIN_SKIP }, /* P3; */
 169                         { 0, USB_OC_PIN_SKIP }, /* P4; */
 170                 },
 171         };
 172
 173         struct romstage_params romstage_params = {
 174                 .pei_data = &pei_data,
 175                 .gpio_map = &mainboard_gpio_map,
 176                 .rcba_config = &rcba_config[0],
 177                 .bist = bist,
 178                 .copy_spd = copy_spd,
 179         };
 180
 181         /* Call into the real romstage main with this board's attributes. */
 182         romstage_common(&romstage_params);
 183 }