src/mainboard/google/peppy/gma.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright 2013 Google Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <types.h>
  17 #include <string.h>
  18 #include <stdlib.h>
  19 #include <device/device.h>
  20 #include <device/device.h>
  21 #include <device/pci_def.h>
  22 #include <device/pci_ops.h>
  23 #include <console/console.h>
  24 #include <delay.h>
  25 #include <pc80/mc146818rtc.h>
  26 #include <arch/acpi.h>
  27 #include <arch/io.h>
  28 #include <arch/interrupt.h>
  29 #include <boot/coreboot_tables.h>
  30 #include <smbios.h>
  31 #include <device/pci.h>
  32 #include <ec/google/chromeec/ec.h>
  33
  34 #include <cpu/x86/tsc.h>
  35 #include <cpu/x86/cache.h>
  36 #include <cpu/x86/mtrr.h>
  37 #include <cpu/x86/msr.h>
  38 #include <edid.h>
  39 #include <drivers/intel/gma/i915.h>
  40 #include <northbridge/intel/haswell/haswell.h>
  41 #include "mainboard.h"
  42
  43 /*
  44  * Here is the rough outline of how we bring up the display:
  45  *  1. Upon power-on Sink generates a hot plug detection pulse thru HPD
  46  *  2. Source determines video mode by reading DPCD receiver capability field
  47  *     (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD
  48  *     0000Dh).
  49  *  3. Sink replies DPCD receiver capability field.
  50  *  4. Source starts EDID read thru I2C-over-AUX.
  51  *  5. Sink replies EDID thru I2C-over-AUX.
  52  *  6. Source determines link configuration, such as MAX_LINK_RATE and
  53  *     MAX_LANE_COUNT. Source also determines which type of eDP Authentication
  54  *     method to use and writes DPCD link configuration field (DPCD 00100h to
  55  *     0010Ah) including eDP configuration set (DPCD 0010Ah).
  56  *  7. Source starts link training. Sink does clock recovery and equalization.
  57  *  8. Source reads DPCD link status field (DPCD 00200h to 0020Bh).
  58  *  9. Sink replies DPCD link status field. If main link is not stable, Source
  59  *     repeats Step 7.
  60  * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video
  61  *     parameters and recovers stream clock.
  62  * 11. Source sends video data.
  63  */
  64
  65 /* how many bytes do we need for the framebuffer?
  66  * Well, this gets messy. To get an exact answer, we have
  67  * to ask the panel, but we'd rather zero the memory
  68  * and set up the gtt while the panel powers up. So,
  69  * we take a reasonable guess, secure in the knowledge that the
  70  * MRC has to overestimate the number of bytes used.
  71  * 8 MiB is a very safe guess. There may be a better way later, but
  72  * fact is, the initial framebuffer is only very temporary. And taking
  73  * a little long is ok; this is done much faster than the AUX
  74  * channel is ready for IO.
  75  */
  76 #define FRAME_BUFFER_BYTES (8*MiB)
  77 /* how many 4096-byte pages do we need for the framebuffer?
  78  * There are hard ways to get this, and easy ways:
  79  * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
  80  * on this chip (and in fact every Intel graphics chip we've seen).
  81  */
  82 #define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
  83
  84
  85 static int i915_init_done = 0;
  86
  87 /* fill the palette. */
  88 static void palette(void)
  89 {
  90         int i;
  91         unsigned long color = 0;
  92
  93         for(i = 0; i < 256; i++, color += 0x010101){
  94                 gtt_write(_LGC_PALETTE_A + (i<<2),color);
  95         }
  96 }
  97
  98 void mainboard_train_link(struct intel_dp *intel_dp)
  99 {
 100         u8 read_val;
 101         u8 link_status[DP_LINK_STATUS_SIZE];
 102
 103         gtt_write(DP_TP_CTL(intel_dp->port),
 104                   DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
 105         gtt_write(DDI_BUF_CTL_A,
 106                   DDI_BUF_CTL_ENABLE|
 107                   DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|0x80000011);
 108
 109         intel_dp_get_training_pattern(intel_dp, &read_val);
 110         intel_dp_set_training_pattern(intel_dp,
 111                                       DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE |
 112                                       DP_SYMBOL_ERROR_COUNT_BOTH);
 113
 114         intel_dp_set_training_lane0(intel_dp,
 115                                     DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
 116         intel_dp_get_link_status(intel_dp, link_status);
 117
 118         gtt_write(DP_TP_CTL(intel_dp->port),
 119                   DP_TP_CTL_ENABLE |
 120                   DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2);
 121
 122         intel_dp_get_training_pattern(intel_dp, &read_val);
 123         intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 |
 124                                       DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
 125         intel_dp_get_link_status(intel_dp, link_status);
 126         intel_dp_get_lane_align_status(intel_dp, &read_val);
 127         intel_dp_get_training_pattern(intel_dp, &read_val);
 128         intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE |
 129                                       DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
 130 }
 131
 132 /* This variable controls whether the test_gfx function below puts up
 133  * color bars or not. In previous revs we ifdef'd the test_gfx function out
 134  * but it's handy, especially when using a JTAG debugger
 135  * to be able to enable and disable a test graphics.
 136  */
 137 int show_test = 0;
 138
 139 static void test_gfx(struct intel_dp *dp)
 140 {
 141         int i;
 142
 143         if (!show_test)
 144                 return;
 145         /* This is a sanity test code which fills the screen with two bands --
 146            green and blue. It is very useful to ensure all the initializations
 147            are made right. Thus, to be used only for testing, not otherwise
 148         */
 149
 150         for (i = 0; i < (dp->edid.mode.va - 4); i++) {
 151                 u32 *l;
 152                 int j;
 153                 u32 tcolor = 0x0ff;
 154                 for (j = 0; j < (dp->edid.mode.ha-4); j++) {
 155                         if (j == (dp->edid.mode.ha/2)) {
 156                                 tcolor = 0xff00;
 157                         }
 158                         l = (u32*)(dp->graphics + i * dp->stride + j * sizeof(tcolor));
 159                         memcpy(l,&tcolor,sizeof(tcolor));
 160                 }
 161         }
 162         printk(BIOS_SPEW, "sleep 10\n");
 163         delay(10);
 164 }
 165
 166 void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
 167 {
 168         u32 ddi_pll_sel = 0;
 169
 170         switch (intel_dp->link_bw) {
 171         case DP_LINK_BW_1_62:
 172                 ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
 173                 break;
 174         case DP_LINK_BW_2_7:
 175                 ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
 176                 break;
 177         case DP_LINK_BW_5_4:
 178                 ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
 179                 break;
 180         default:
 181                 printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw);
 182                 return;
 183         }
 184
 185         gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
 186 }
 187
 188 int panel_lightup(struct intel_dp *dp, unsigned int init_fb)
 189 {
 190         int i;
 191         int edid_ok;
 192         int pixels = FRAME_BUFFER_BYTES/64;
 193
 194         gtt_write(PCH_PP_CONTROL,0xabcd000f);
 195         delay(1);
 196
 197         void runio(struct intel_dp *dp);
 198         /* hard codes -- stuff you can only know from the mainboard */
 199         dp->gen = 8; // This is gen 8 which we believe is Haswell
 200         dp->is_haswell = 1;
 201         dp->DP = 0x2;
 202         dp->pipe = PIPE_A;
 203         dp->port = PORT_A;
 204         dp->plane = PLANE_A;
 205         dp->pipe_bits_per_pixel = 24;
 206         dp->type = INTEL_OUTPUT_EDP;
 207         dp->output_reg = DP_A;
 208         /* observed from YABEL. */
 209         dp->aux_clock_divider = 0xe1;
 210         dp->precharge = 3;
 211
 212         /* 1. Normal mode: Set the first page to zero and make
 213            all GTT entries point to the same page
 214            2. Developer/Recovery mode: Set up a tasteful color
 215               so people know we are alive. */
 216         if (init_fb || show_test) {
 217                 set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase,
 218                                         4096);
 219                 memset((void *)dp->graphics, 0x55, FRAME_BUFFER_PAGES*4096);
 220         } else {
 221                 set_translation_table(0, FRAME_BUFFER_PAGES, dp->physbase, 0);
 222                 memset((void*)dp->graphics, 0, 4096);
 223         }
 224
 225         dp->address = 0x50;
 226
 227         if ( !intel_dp_get_dpcd(dp) )
 228                 goto fail;
 229
 230         intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL);
 231         for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){
 232                 if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ,
 233                                         0x50, &dp->rawedid[i]) < 0)
 234                         break;
 235                 dp->edidlen++;
 236         }
 237
 238         edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid);
 239
 240         printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
 241
 242         compute_display_params(dp);
 243
 244         printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",
 245                dp->edid.mode.pixel_clock, dp->edid.link_clock);
 246
 247         intel_ddi_set_pipe_settings(dp);
 248
 249         runio(dp);
 250
 251         palette();
 252
 253         pixels = dp->edid.mode.ha * (dp->edid.mode.va-4) * 4;
 254         printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.mode.ha, dp->edid.mode.va);
 255         test_gfx(dp);
 256
 257         set_vbe_mode_info_valid(&dp->edid, (uintptr_t)dp->graphics);
 258         i915_init_done = 1;
 259         return 1;
 260
 261 fail:
 262         printk(BIOS_SPEW, "Graphics could not be started;");
 263         /* unclear we will *ever* want to do this. */
 264         if (0){
 265                 printk(BIOS_SPEW, "Turn off power and wait ...");
 266                 gtt_write(PCH_PP_CONTROL,0xabcd0000);
 267                 udelay(600000);
 268                 gtt_write(PCH_PP_CONTROL,0xabcd000f);
 269         }
 270         printk(BIOS_SPEW, "Returning.\n");
 271         return 0;
 272 }