src/mainboard/google/parrot/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2010 coresystems GmbH
   5  * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <stdint.h>
  18 #include <string.h>
  19 #include <lib.h>
  20 #include <timestamp.h>
  21 #include <arch/io.h>
  22 #include <device/pci_def.h>
  23 #include <device/pnp_def.h>
  24 #include <cpu/x86/lapic.h>
  25 #include <pc80/mc146818rtc.h>
  26 #include <arch/acpi.h>
  27 #include <cbmem.h>
  28 #include <console/console.h>
  29 #include <northbridge/intel/sandybridge/sandybridge.h>
  30 #include <northbridge/intel/sandybridge/raminit.h>
  31 #include <southbridge/intel/bd82x6x/pch.h>
  32 #include <southbridge/intel/bd82x6x/gpio.h>
  33 #include <arch/cpu.h>
  34 #include <cpu/x86/bist.h>
  35 #include <cpu/x86/msr.h>
  36 #include <halt.h>
  37 #include "gpio.h"
  38 #include <cbfs.h>
  39 #include <tpm.h>
  40 #include "ec/compal/ene932/ec.h"
  41
  42 static void pch_enable_lpc(void)
  43 {
  44         /* Parrot EC Decode Range Port60/64, Port62/66 */
  45         /* Enable EC, PS/2 Keyboard/Mouse */
  46         pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
  47
  48         /* Map EC_IO decode to the LPC bus */
  49         pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (EC_IO & ~3) | 0x00040001);
  50
  51         /* Map EC registers 68/6C decode to the LPC bus */
  52         pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001);
  53 }
  54
  55 static void rcba_config(void)
  56 {
  57         u32 reg32;
  58
  59         /*
  60          *             GFX    INTA -> PIRQA (MSI)
  61          * D28IP_P2IP  WLAN   INTA -> PIRQB
  62          * D28IP_P3IP  ETH0   INTC -> PIRQD
  63          * D29IP_E1P   EHCI1  INTA -> PIRQE
  64          * D26IP_E2P   EHCI2  INTA -> PIRQE
  65          * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
  66          * D31IP_SMIP  SMBUS  INTB -> PIRQG
  67          * D31IP_TTIP  THRT   INTC -> PIRQH
  68          * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
  69          *
  70          * Trackpad DVT PIRQA (16)
  71          * Trackpad DVT PIRQE (20)
  72          */
  73
  74         /* Device interrupt pin register (board specific) */
  75         RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
  76                 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
  77         RCBA32(D30IP) = (NOINT << D30IP_PIP);
  78         RCBA32(D29IP) = (INTA << D29IP_E1P);
  79         RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
  80                 (INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
  81                 (NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) |
  82                 (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
  83         RCBA32(D27IP) = (INTA << D27IP_ZIP);
  84         RCBA32(D26IP) = (INTA << D26IP_E2P);
  85         RCBA32(D25IP) = (NOINT << D25IP_LIP);
  86         RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
  87
  88         /* Device interrupt route registers */
  89         DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
  90         DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
  91         DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
  92         DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
  93         DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
  94         DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
  95         DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
  96
  97         /* Enable IOAPIC (generic) */
  98         RCBA16(OIC) = 0x0100;
  99         /* PCH BWG says to read back the IOAPIC enable register */
 100         (void) RCBA16(OIC);
 101
 102         /* Disable unused devices (board specific) */
 103         reg32 = RCBA32(FD);
 104         reg32 |= PCH_DISABLE_ALWAYS;
 105         /* Disable PCI bridge so MRC does not probe this bus */
 106         reg32 |= PCH_DISABLE_P2P;
 107         RCBA32(FD) = reg32;
 108 }
 109
 110 #include <cpu/intel/romstage.h>
 111 void main(unsigned long bist)
 112 {
 113         int boot_mode = 0;
 114         int cbmem_was_initted;
 115
 116         struct pei_data pei_data = {
 117                 .pei_version = PEI_VERSION,
 118                 .mchbar = (uintptr_t)DEFAULT_MCHBAR,
 119                 .dmibar = (uintptr_t)DEFAULT_DMIBAR,
 120                 .epbar = DEFAULT_EPBAR,
 121                 .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
 122                 .smbusbar = SMBUS_IO_BASE,
 123                 .wdbbar = 0x4000000,
 124                 .wdbsize = 0x1000,
 125                 .hpet_address = CONFIG_HPET_ADDRESS,
 126                 .rcba = (uintptr_t)DEFAULT_RCBABASE,
 127                 .pmbase = DEFAULT_PMBASE,
 128                 .gpiobase = DEFAULT_GPIOBASE,
 129                 .thermalbase = 0xfed08000,
 130                 .system_type = 0, // 0 Mobile, 1 Desktop/Server
 131                 .tseg_size = CONFIG_SMM_TSEG_SIZE,
 132                 .spd_addresses = { 0xA0, 0x00,0xA4,0x00 },
 133                 .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
 134                 .ec_present = 1,
 135                 // 0 = leave channel enabled
 136                 // 1 = disable dimm 0 on channel
 137                 // 2 = disable dimm 1 on channel
 138                 // 3 = disable dimm 0+1 on channel
 139                 .dimm_channel0_disabled = 2,
 140                 .dimm_channel1_disabled = 2,
 141                 .max_ddr3_freq = 1600,
 142                 .usb_port_config = {
 143                         /* Empty and onboard Ports 0-7, set to un-used pin OC3 */
 144                         { 0, 3, 0x0000 }, /* P0: Empty */
 145                         { 1, 0, 0x0040 }, /* P1: Left USB 1  (OC0) */
 146                         { 1, 1, 0x0040 }, /* P2: Left USB 2  (OC1) */
 147                         { 1, 1, 0x0040 }, /* P3: Left USB 3  (OC1) */
 148                         { 0, 3, 0x0000 }, /* P4: Empty */
 149                         { 0, 3, 0x0000 }, /* P5: Empty */
 150                         { 0, 3, 0x0000 }, /* P6: Empty */
 151                         { 0, 3, 0x0000 }, /* P7: Empty */
 152                         /* Empty and onboard Ports 8-13, set to un-used pin OC4 */
 153                         { 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */
 154                         { 0, 4, 0x0000 }, /* P9: Empty */
 155                         { 1, 4, 0x0040 }, /* P10: Camera (no OC) */
 156                         { 0, 4, 0x0000 }, /* P11: Empty */
 157                         { 0, 4, 0x0000 }, /* P12: Empty */
 158                         { 0, 4, 0x0000 }, /* P13: Empty */
 159                 },
 160         };
 161
 162         timestamp_init(get_initial_timestamp());
 163         timestamp_add_now(TS_START_ROMSTAGE);
 164
 165         if (bist == 0)
 166                 enable_lapic();
 167
 168         pch_enable_lpc();
 169
 170         /* Enable GPIOs */
 171         pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
 172         pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
 173         setup_pch_gpios(&parrot_gpio_map);
 174
 175         /* Initialize console device(s) */
 176         console_init();
 177
 178         /* Halt if there was a built in self test failure */
 179         report_bist_failure(bist);
 180
 181         if (MCHBAR16(SSKPD) == 0xCAFE) {
 182                 printk(BIOS_DEBUG, "soft reset detected\n");
 183                 boot_mode = 1;
 184
 185                 /* System is not happy after keyboard reset... */
 186                 printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
 187                 outb(0x6, 0xcf9);
 188                 halt();
 189         }
 190
 191         /* Perform some early chipset initialization required
 192          * before RAM initialization can work
 193          */
 194         sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
 195         printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
 196
 197         boot_mode = southbridge_detect_s3_resume() ? 2 : 0;
 198
 199         post_code(0x38);
 200         /* Enable SPD ROMs and DDR-III DRAM */
 201         enable_smbus();
 202
 203         /* Prepare USB controller early in S3 resume */
 204         if (boot_mode == 2)
 205                 enable_usb_bar();
 206
 207         post_code(0x39);
 208
 209         post_code(0x3a);
 210         pei_data.boot_mode = boot_mode;
 211         timestamp_add_now(TS_BEFORE_INITRAM);
 212         sdram_initialize(&pei_data);
 213
 214         timestamp_add_now(TS_AFTER_INITRAM);
 215         post_code(0x3c);
 216
 217         rcba_config();
 218         post_code(0x3d);
 219
 220         quick_ram_check();
 221         post_code(0x3e);
 222
 223         cbmem_was_initted = !cbmem_recovery(boot_mode==2);
 224         if (boot_mode!=2)
 225                 save_mrc_data(&pei_data);
 226
 227         if (boot_mode==2 && !cbmem_was_initted) {
 228                 /* Failed S3 resume, reset to come up cleanly */
 229                 outb(0x6, 0xcf9);
 230                 halt();
 231         }
 232         northbridge_romstage_finalize(boot_mode==2);
 233
 234         post_code(0x3f);
 235         if (CONFIG_LPC_TPM) {
 236                 init_tpm(boot_mode == 2);
 237         }
 238 }