2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007-2008 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
16 # -----------------------------------------------------------------
19 # -----------------------------------------------------------------
21 # -----------------------------------------------------------------
23 # -----------------------------------------------------------------
25 #96 4 r 0 status_c_rsvd
30 # -----------------------------------------------------------------
32 #104 7 r 0 status_d_rsvd
33 #111 1 r 0 valid_cmos_ram
34 # -----------------------------------------------------------------
35 # Diagnostic Status Register
38 # -----------------------------------------------------------------
39 0 120 r 0 reserved_memory
42 # -----------------------------------------------------------------
43 # RTC_BOOT_BYTE (coreboot hardcoded)
49 # -----------------------------------------------------------------
50 # coreboot config options: console
55 # coreboot config options: cpu
56 400 1 e 2 hyper_threading
59 # coreboot config options: southbridge
61 409 2 e 7 power_on_after_fail
65 # coreboot config options: bootloader
69 # coreboot config options: northbridge
70 544 3 e 11 gfx_uma_size
74 # SandyBridge MRC Scrambler Seed values
75 896 32 r 0 mrc_scrambler_seed
76 928 32 r 0 mrc_scrambler_seed_s3
78 # coreboot config options: check sums
80 #1000 24 r 0 amd_reserved
82 # -----------------------------------------------------------------
122 # -----------------------------------------------------------------