src/mainboard/google/parrot/chromeos.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011-2012 The ChromiumOS Authors.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <console/console.h>
  17 #include <string.h>
  18 #include <bootmode.h>
  19 #include <arch/io.h>
  20 #include <device/device.h>
  21 #include <device/pci.h>
  22
  23 #include <southbridge/intel/bd82x6x/pch.h>
  24 #include <ec/compal/ene932/ec.h>
  25 #include "ec.h"
  26
  27
  28 #ifndef __PRE_RAM__
  29 #include <boot/coreboot_tables.h>
  30
  31 #define GPIO_COUNT      6
  32
  33 void fill_lb_gpios(struct lb_gpios *gpios)
  34 {
  35         device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
  36         u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
  37         u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
  38
  39         if (!gpio_base)
  40                 return;
  41
  42         gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
  43         gpios->count = GPIO_COUNT;
  44
  45         /* Write Protect: GPIO70 active high */
  46         gpios->gpios[0].port = 70;
  47         gpios->gpios[0].polarity = ACTIVE_LOW;
  48         gpios->gpios[0].value = !get_write_protect_state();
  49         strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH);
  50
  51         /* Recovery: Virtual GPIO in the EC (Servo GPIO68 active low) */
  52         gpios->gpios[1].port = -1;
  53         gpios->gpios[1].polarity = ACTIVE_HIGH;
  54         gpios->gpios[1].value = get_recovery_mode_switch();
  55         strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
  56
  57         /* Developer: Virtual GPIO in the EC ( Servo GPIO17 active low) */
  58         gpios->gpios[2].port = -1;
  59         gpios->gpios[2].polarity = ACTIVE_HIGH;
  60         gpios->gpios[2].value = get_developer_mode_switch();
  61         strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
  62
  63         /* Lid switch GPIO active high (open). */
  64         gpios->gpios[3].port = 15;
  65         gpios->gpios[3].polarity = ACTIVE_HIGH;
  66         gpios->gpios[3].value = get_lid_switch();
  67         strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
  68
  69         /* Power Button */
  70         gpios->gpios[4].port = 101;
  71         gpios->gpios[4].polarity = ACTIVE_LOW;
  72         gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1;
  73         strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
  74
  75         /* Did we load the VGA Option ROM? */
  76         gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
  77         gpios->gpios[5].polarity = ACTIVE_HIGH;
  78         gpios->gpios[5].value = gfx_get_init_done();
  79         strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
  80
  81 }
  82 #endif
  83
  84 int get_lid_switch(void)
  85 {
  86         device_t dev;
  87 #ifdef __PRE_RAM__
  88         dev = PCI_DEV(0, 0x1f, 0);
  89 #else
  90         dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
  91 #endif
  92         u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
  93
  94         if (!gpio_base)
  95                 return 0;
  96
  97         u32 gp_lvl = inl(gpio_base + GP_LVL);
  98         return (gp_lvl >> 15) & 1;
  99 }
 100
 101 int get_developer_mode_switch(void)
 102 {
 103         device_t dev;
 104 #ifdef __PRE_RAM__
 105         dev = PCI_DEV(0, 0x1f, 0);
 106 #else
 107         dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
 108 #endif
 109         u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
 110
 111         if (!gpio_base)
 112                 return(0);
 113
 114 /*
 115  * Dev mode is controled by EC and uboot stores a flag in TPM. This GPIO is only
 116  * for the debug header. It is AND'd to the EC request.
 117  */
 118
 119         u32 gp_lvl = inl(gpio_base + GP_LVL);
 120         printk(BIOS_DEBUG,"DEV MODE GPIO 17: %x\n", !((gp_lvl >> 17) & 1));
 121
 122         /* GPIO17, active low -- return active high reading and let
 123          * it be inverted by the caller if needed. */
 124         return !((gp_lvl >> 17) & 1);
 125 }
 126
 127 int get_write_protect_state(void)
 128 {
 129         device_t dev;
 130 #ifdef __PRE_RAM__
 131         dev = PCI_DEV(0, 0x1f, 0);
 132 #else
 133         dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
 134 #endif
 135         u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
 136
 137         if (!gpio_base)
 138                 return 0;
 139
 140         u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
 141
 142         return !((gp_lvl3 >> (70 - 64)) & 1);
 143 }
 144
 145 int get_recovery_mode_switch(void)
 146 {
 147         u8 rec_mode;
 148
 149         device_t dev;
 150 #ifdef __PRE_RAM__
 151         dev = PCI_DEV(0, 0x1f, 0);
 152 #else
 153         dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
 154 #endif
 155         u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
 156
 157         if (!gpio_base)
 158                 return(0);
 159
 160         /* GPIO68, active low. For Servo support
 161          * Treat as active high and let the caller invert if needed. */
 162         u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
 163         rec_mode = !((gp_lvl3 >> (68 - 64)) & 1);
 164         printk(BIOS_DEBUG,"REC MODE GPIO 68: %x\n", rec_mode);
 165
 166         return (rec_mode);
 167 }
 168
 169 int parrot_ec_running_ro(void)
 170 {
 171         device_t dev;
 172 #ifdef __PRE_RAM__
 173         dev = PCI_DEV(0, 0x1f, 0);
 174 #else
 175         dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
 176 #endif
 177         u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
 178
 179         if (!gpio_base)
 180                 return(0);
 181
 182         /* GPIO68 EC_RW is active low.
 183          * Treat as active high and let the caller invert if needed. */
 184         u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
 185         return !((gp_lvl3 >> (68 - 64)) & 1);
 186 }